Freescale Semiconductor Data Sheet: Technical Data K70 Sub-Family Document Number: K70P256M150SF3 Rev. 5, 10/2013 K70P256M150SF3 Supports the following: MK70FX512VMJ15, MK70FN1M0VMJ15 Features • Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C • Performance – Up to 150 MHz ARM Cortex-M4 core with DSP instructions delivering 1.
• Communication interfaces – Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability – USB high-/full-/low-speed On-the-Go controller with ULPI interface – USB high-/full-/low-speed On-the-Go controller with on-chip high speed transceiver – USB full-/low-speed On-the-Go controller with on-chip transceiver – USB Device Charger detect – Two Controller Area Network (CAN) modules – Three SPI modules – Two I2C modules – Six UART modules – Secure Digital host controller (
Table of Contents 1 Ordering parts...........................................................................5 5.4.2 Thermal attributes...............................................26 1.1 Determining valid orderable parts......................................5 5.5 Power sequencing.............................................................27 2 Part identification......................................................................5 6 Peripheral operating requirements and behaviors..................
6.8.12 I2S/SAI switching specifications.........................75 8 Pinout........................................................................................86 6.9 Human-machine interfaces (HMI)......................................82 8.1 Pins with active pull control after reset..............................86 6.9.1 TSI electrical specifications................................82 8.2 K61 Signal Multiplexing and Pin Assignments..................86 6.9.2 LCDC electrical specifications..........
Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: PK70 and MK70 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.
Terminology and guidelines Field Description Values T Temperature range (°C) • V = –40 to 105 • C = –40 to 85 PP Package identifier • MJ = 256 MAPBGA (17 mm x 17 mm) CC Maximum CPU frequency (MHz) • 15 = 150 MHz N Packaging type • R = Tape and reel • (Blank) = Trays 2.4 Example This is an example part number: MK70FN1M0VMJ15 3 Terminology and guidelines 3.
Terminology and guidelines 3.2.1 Example This is an example of an operating behavior: Symbol IWP Description Min. Digital I/O weak pullup/ 10 pulldown current Max. 130 Unit µA 3.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 Example This is an example of an attribute: Symbol CIN_D Description Input capacitance: digital pins Min. — Max. 7 Unit pF 3.
Terminology and guidelines 3.5 Result of exceeding a rating 40 Failures in time (ppm) 30 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 20 10 0 Operating rating Measured characteristic 3.6 Relationship between ratings and operating requirements g( Op era tin g in rat ) in. m m ire g tin era Op u req t en in. (m ) m ire Op g tin era u req t en (m ax .) x.
Terminology and guidelines 3.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. 3.8.
Ratings 3.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V 4 Ratings 4.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2.
General Symbol VCDM ILAT Description Min. Max. Unit Notes Electrostatic discharge voltage, charged-device model -500 Latch-up current at ambient temperature of 105°C -100 +500 V 2 +100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2.
General 5.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Figure 1. Input signal measurement reference All digital I/O switching characteristics assume: 1. output pins • have CL=30pF loads, • are configured for fast slew rate (PORTx_PCRn[SRE]=0), and • are configured for high drive strength (PORTx_PCRn[DSE]=1) 2.
General Table 1. Voltage and current operating requirements (continued) Symbol Description VSS – VSSA VSS-to-VSSA differential voltage VBAT VIH RTC battery supply voltage Input high voltage (digital pins except Tamper pins and DDR pins) • 2.7 V ≤ VDD ≤ 3.6 V • 1.7 V ≤ VDD ≤ 2.7 V VIL Input low voltage (digital pins except Tamper pins and DDR pins) • 2.7 V ≤ VDD ≤ 3.6 V Min. Max. Unit –0.1 0.1 V 1.71 3.6 V 0.7 × VDD — V 0.75 × VDD — V — 0.35 × VDD V — 0.3 × VDD V VREF_DDR + 0.
General 1. For DDR1/DDR2, connect VREF_DDR to the same reference voltage used for the memory. For LPDDR1, connect VREF_DDR to the VDD_DDR voltage. 2. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads.
General 1. Rising thresholds are falling threshold + hysteresis voltage Table 3. VBAT power operating requirements Symbol Description VPOR_VBAT Falling VBAT supply POR detect voltage Min. Typ. Max. Unit 0.8 1.1 1.5 V Notes 5.2.3 Voltage and current operating behaviors Table 4. Voltage and current operating behaviors Symbol Min. Typ. • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA VDD – 0.5 — • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA VDD – 0.5 — • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA VDD – 0.5 — • 1.
General Table 4. Voltage and current operating behaviors (continued) Symbol Description IOH_Tamper Output high current total for Tamper pins VOL Min. Typ. Max. Unit — — 100 mA 0.5 V 0.5 V 0.5 V 0.5 V Output low voltage — high drive strength — • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10 mA — • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 5 mA — — Output low voltage — low drive strength IOLT — • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA — • 1.71 V ≤ VDD ≤ 2.
General Table 4. Voltage and current operating behaviors (continued) Symbol IIND Description Min. Typ. Max. Unit Input leakage current, digital pins Notes 2, 3 • VSS ≤ VIN ≤ VIL • All digital pins — 0.002 0.5 μA — 0.002 0.5 μA — 0.004 1 μA • VIN = VDD • All digital pins except PTD7 • PTD7 IIND Input leakage current, digital pins 2, 3, 4 • VIL < VIN < VDD IIND • VDD = 3.6 V — 18 26 μA • VDD = 3.0 V — 12 19 μA • VDD = 2.5 V — 8 13 μA • VDD = 1.
General Figure 2. 5 V Tolerant Input IIND Parameter 5.2.4 Power mode transition operating behaviors All specifications except tPOR, and VLLSx→RUN recovery times in the following table assume this clock configuration: • • • • • CPU and system clocks = 150 MHz Bus clock = 75 MHz FlexBus clock = 50 MHz Flash clock = 25 MHz MCG mode: FEI Table 5. Power mode transition operating behaviors Symbol tPOR Description Min. Max. Unit After a POR event, amount of time from the point VDD reaches 1.
General 5.2.5 Power consumption operating behaviors Table 6. Power consumption operating behaviors Symbol IDDA IDD_RUN IDD_RUN Description Analog supply current Min. Typ. Max. Unit Notes — — See note mA 1 Run mode current — all peripheral clocks disabled, code executing from flash 2 • @ 1.8V — 59.6 180 mA • @ 3.0V — 59.6 185 mA Run mode current — all peripheral clocks enabled, code executing from flash 3 • @ 1.8V — 89.9 205 mA • @ 3.0V — 89.
General Table 6. Power consumption operating behaviors (continued) Symbol IDD_VLLS2 IDD_VLLS1 IDD_VBAT Description Min. Typ. Max. Unit • @ –40 to 25°C — 3.2 14 μA • @ 70°C — 11.8 40 μA • @ 105°C — 51.2 60 μA • @ –40 to 25°C — 2.8 12 μA • @ 70°C — 8.7 29 μA • @ 105°C — 39.3 43 μA Notes Very low-leakage stop mode 2 current at 3.0 V Very low-leakage stop mode 1 current at 3.0 V Average current when CPU is not accessing RTC registers at 3.0 V 8 • @ –40 to 25°C — 0.
General Figure 3. Run mode supply current vs. core frequency K70 Sub-Family Data Sheet, Rev. 5, 10/2013. Freescale Semiconductor, Inc.
General Figure 4. VLPR mode supply current vs. core frequency 5.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors for 256MAPBGA Symbol Description Frequency band (MHz) Typ. Unit Notes 1, 2, 3 VRE1 Radiated emissions voltage, band 1 0.15–50 21 dBμV VRE2 Radiated emissions voltage, band 2 50–150 24 dBμV VRE3 Radiated emissions voltage, band 3 150–500 29 dBμV VRE4 Radiated emissions voltage, band 4 500–1000 28 dBμV 1.
General 5.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.freescale.com. 2. Perform a keyword search for “EMC design.” 5.2.8 Capacitance attributes Table 8. Capacitance attributes Symbol Description Min. Max.
General Table 9. Device clock specifications (continued) Symbol Description Min. Max. Unit fSYS System and core clock — 4 MHz fBUS Bus clock — 4 MHz FlexBus clock — 4 MHz fFLASH Flash clock — 0.5 MHz fLPTMR LPTMR clock — 4 MHz FB_CLK Notes 1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. 5.3.
General Table 10. General switching specifications (continued) Symbol Description Min. Max. Unit Port rise and fall time (low drive strength) Notes 5 • Slew disabled • 1.71 ≤ VDD ≤ 2.7V — 14 ns • 2.7 ≤ VDD ≤ 3.6V — 8 ns • 1.71 ≤ VDD ≤ 2.7V — 36 ns • 2.7 ≤ VDD ≤ 3.6V — 24 ns • Slew enabled tio50 Port rise and fall time (high drive strength) 6 • Slew disabled • 1.71 ≤ VDD ≤ 2.7V — 7 ns — • 2.7 ≤ VDD ≤ 3.6V — 3 ns — • 1.71 ≤ VDD ≤ 2.7V — 28 ns — • 2.7 ≤ VDD ≤ 3.
General 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 75 pF load 5. 15 pF load 6.
Peripheral operating requirements and behaviors Board type Symbol Description Unit Notes — RθJC Thermal 8 resistance, junction to case °C/W 5 — ΨJT Thermal 2 characterization parameter, junction to package top outside center (natural convection) °C/W 6 1. 2. 3. 4. 5. 6.
Peripheral operating requirements and behaviors 6.1 Core modules 6.1.1 Debug trace timing specifications Table 12. Debug trace operating behaviors Symbol Description Min. Max. Unit Tcyc Clock period Frequency dependent MHz Twl Low pulse width 2 — ns Twh High pulse width 2 — ns Tr Clock and data rise time — 3 ns Tf Clock and data fall time — 3 ns Ts Data setup 3 — ns Th Data hold 2 — ns Figure 5.
Peripheral operating requirements and behaviors Table 13. JTAG limited voltage range electricals (continued) Symbol J1 Description Min. Max.
Peripheral operating requirements and behaviors Table 14. JTAG full voltage range electricals (continued) Symbol Description Min. Max. Unit J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1.4 — ns J11 TCLK low to TDO data valid — 22.1 ns J12 TCLK low to TDO high-Z — 22.
Peripheral operating requirements and behaviors TCLK J9 TDI/TMS J10 Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 9. Test Access Port timing TCLK J14 J13 TRST Figure 10. TRST timing 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules K70 Sub-Family Data Sheet, Rev. 5, 10/2013. Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors 6.3.1 MCG specifications Table 15. MCG specifications Symbol Description Min. Typ. Max. Unit — 32.768 — kHz 31.25 — 39.0625 kHz Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM and SCFTRIM — ± 0.3 ± 0.6 %fdco 1 Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM only — ± 0.2 ± 0.
Peripheral operating requirements and behaviors Table 15. MCG specifications (continued) Symbol Jcyc_fll Description FLL period jitter • fVCO = 48 MHz • fVCO = 98 MHz tfll_acquire FLL target frequency acquisition time Min. Typ. Max.
Peripheral operating requirements and behaviors 9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. Accumulated jitter depends on VCO frequency and VDIV. 6.3.2 Oscillator electrical specifications 6.3.2.1 Oscillator DC electrical specifications Table 16. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.
Peripheral operating requirements and behaviors Table 16. Oscillator DC electrical specifications (continued) Symbol RS Description Min. Typ. Max. Unit Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Notes Series resistor — high-frequency, high-gain mode (HGO=1) Vpp5 1. 2. 3. 4. 5.
Peripheral operating requirements and behaviors Table 17. Oscillator frequency specifications (continued) Symbol tcst Description Min. Typ. Max. Unit Notes Crystal startup time — 32 kHz low-frequency, low-power mode (HGO=0) — 1000 — ms 4, 5 Crystal startup time — 32 kHz low-frequency, high-gain mode (HGO=1) — 500 — ms Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) — 0.
Peripheral operating requirements and behaviors Table 19. 32 kHz oscillator frequency specifications (continued) Symbol tstart Description Crystal start-up time vec_extal32 Externally provided input clock amplitude Min. Typ. Max. Unit Notes — 1000 — ms 1 700 — VBAT mV 2, 3 1. Proper PC board layout procedures must be followed to achieve specifications. 2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.
Peripheral operating requirements and behaviors Table 21. Flash command timing specifications (continued) Symbol Description Min. Typ. Max.
Peripheral operating requirements and behaviors Table 21. Flash command timing specifications (continued) Symbol Description Min. Typ. Max.
Peripheral operating requirements and behaviors Table 23. NVM reliability specifications (continued) Symbol Description Min. Typ.1 Max.
Peripheral operating requirements and behaviors • EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with Program Partition command • EEESPLIT — FlexRAM split factor for subsystem; entered with the Program Partition command • EEESIZE — allocated FlexRAM based on DEPART; entered with Program Partition command • Write_efficiency — • 0.25 for 8-bit writes to FlexRAM • 0.50 for 16-bit or 32-bit writes to FlexRAM • nnvmcycee — EEPROM-backup cycling endurance Figure 11.
Peripheral operating requirements and behaviors Table 24. EzPort switching specifications (continued) Num Description Min. Max.
Peripheral operating requirements and behaviors which are defined as: T NFC = T L + T H = T input clock SCALER The SCALER value is derived from the fractional divider specified in the SIM's CLKDIV4 register: SCALER = SIM_CLKDIV4[NFCFRAC] + 1 SIM_CLKDIV4[NFCDIV] + 1 In case the reciprocal of SCALER is an integer, the duty cycle of NFC clock is 50%, means TH = TL.
Peripheral operating requirements and behaviors Table 25. NFC specifications (continued) Num Description Min. Max.
Peripheral operating requirements and behaviors tCS tCH tWC NFC_CEn tWP tWH tDS tDH NFC_WE NFC_IOn data data data Figure 15. Write data latch cycle timing tCH tRC NFC_CEn tREH tRP NFC_RE tIS NFC_IOn data data data tRR NFC_RB Figure 16. Read data latch cycle timing in non-fast mode tCH tRC NFC_CEn tRP tREH NFC_RE tIS NFC_IOn data data data tRR NFC_RB Figure 17. Read data latch cycle timing in fast mode 6.4.
Peripheral operating requirements and behaviors Table 26. DDR controller — AC timing specifications Symbol Description Min. Max. Unit Frequency of operation tDDRCK VOX-AC 83.3 150 MHz • DDR2 1251 150 MHz 50 150 MHz • DDR1 6.6 12 ns • DDR2 6.6 8 ns • LPDDR 6.6 20 ns 0.5 x VDD_DDR – 0.2 V 0.5 x VDD_DDR + 0.2 V V 0.5 x VDD_DDR – 0.125 V 0.5 x VDD_DDR + 0.125 V Clock period DDRCK AC differential cross point voltage • DDR1 • DDR2 • LPDDR 1. 2. 3. 4. 5. 6. 7. 8.
Peripheral operating requirements and behaviors 1 2 3 4 5 6 7 8 tDDRCKH tDDRCK 9 10 tDDRCKL DDR_CLK DDR__CLK tCMH tCMV DDR_CSn, DDR_WE DDR_CAS, DDR_RAS DDR_An CMD CMD ROW COL tDQSS DDR_DQSn tQH tQS DDR_DMn DDR_DQn WD1 WD2 WD3 WD4 Figure 18. DDR write timing 1 2 3 4 5 6 7 8 tDDRCHH tDDRCK 9 10 11 12 tDDRCKL DDR_CLK tCMH DDR__CLK tCMV DDR_CSn, DDR_WE CMD CMD ROW COL DDR_CAS, DDR_RAS DDR_An CL=2.5 DDR_DQS (CL=2.5) DQS read preamble DDR_DQn (CL=2.
Peripheral operating requirements and behaviors Figure 20. DDR read timing, DQ vs. DQS 6.4.5 Flexbus switching specifications All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency.
Peripheral operating requirements and behaviors Table 28. Flexbus full voltage range switching specifications (continued) Num Description Min. Max. Unit Notes FB4 Data and FB_TA input setup 13.7 — ns 2 FB5 Data and FB_TA input hold 0.5 — ns 2 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA.
Peripheral operating requirements and behaviors FB1 FB_CLK FB2 FB3 FB_A[Y] FB_D[X] Address Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB4 FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 22. FlexBus write timing diagram 6.5 Security and integrity modules 6.5.1 DryIce Tamper Electrical Specifications Information about security-related modules is not included in this document and is available only after a nondisclosure agreement (NDA) has been signed.
Peripheral operating requirements and behaviors 6.6 Analog 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 29 and Table 30 are achievable on the differential pins ADCx_DP0, ADCx_DM0. The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are not direct device pins. Accuracy specifications for these pins are defined in Table 31 and Table 32. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.
Peripheral operating requirements and behaviors Table 29. 16-bit ADC operating conditions (continued) Symbol Crate Description Conditions ADC conversion rate ≤ 13-bit modes Min. Typ.1 Max. Unit Notes 5 No ADC hardware averaging 20.000 — 818.330 Ksps Continuous conversions enabled, subsequent conversion time Crate ADC conversion rate 16-bit mode 5 No ADC hardware averaging 37.037 — 461.467 Ksps Continuous conversions enabled, subsequent conversion time 1.
Peripheral operating requirements and behaviors Table 30. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description IDDA_ADC Supply current fADACK ADC asynchronous clock source Sample Time TUE DNL INL Min. Typ.2 Max. Unit Notes 0.215 — 1.7 mA 3 • ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz • ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz tADACK = 1/ fADACK • ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz • ADLPC = 0, ADHSC = 1 4.4 6.2 9.
Peripheral operating requirements and behaviors Table 30. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol Description EIL Input leakage error Conditions1. Min. Typ.2 Max. IIn × RAS Unit Notes mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) VTEMP25 Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 Temp sensor voltage 25 °C 706 716 726 mV 8 1.
Peripheral operating requirements and behaviors Figure 25. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode 6.6.1.3 16-bit ADC with PGA operating conditions Table 31. 16-bit ADC with PGA operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 — 3.
Peripheral operating requirements and behaviors Table 31. 16-bit ADC with PGA operating conditions (continued) Symbol Crate Description Conditions ADC conversion rate ≤ 13 bit modes Min. Typ.1 Max. Unit Notes 18.484 — 450 Ksps 7 37.037 — 250 Ksps 8 No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 16 bit modes No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 1. Typical values assume VDDA = 3.
Peripheral operating requirements and behaviors Table 32. 16-bit ADC with PGA characteristics (continued) Symbol G BW Description Gain4 Input signal bandwidth Min. Typ.1 Max. • PGAG=0 0.95 1 1.05 • PGAG=1 1.9 2 2.1 • PGAG=2 3.8 4 4.2 • PGAG=3 7.6 8 8.4 • PGAG=4 15.2 16 16.6 • PGAG=5 30.0 31.6 33.2 • PGAG=6 58.8 63.3 67.
Peripheral operating requirements and behaviors Table 32. 16-bit ADC with PGA characteristics (continued) Symbol THD SFDR ENOB SINAD Description Conditions Min. Typ.1 Max. Unit Notes 16-bit differential mode, Average=32, fin=100Hz Total harmonic distortion • Gain=1 85 100 — dB • Gain=64 49 95 — dB Spurious free dynamic range • Gain=1 85 105 — dB • Gain=64 53 88 — dB Effective number of bits • Gain=1, Average=4 11.6 13.4 — bits • Gain=1, Average=8 8.0 13.
Peripheral operating requirements and behaviors Table 33. Comparator and 6-bit DAC electrical specifications (continued) Symbol VH Description Min. Typ. Max. Unit • CR0[HYSTCTR] = 00 — 5 — mV • CR0[HYSTCTR] = 01 — 10 — mV • CR0[HYSTCTR] = 10 — 20 — mV • CR0[HYSTCTR] = 11 — 30 — mV Analog comparator hysteresis1 VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.
Peripheral operating requirements and behaviors 0.08 0.07 0.06 HYSTCTR Setting CM P Hystereris (V) 0.05 00 0.04 01 10 11 0.03 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 Vin level (V) 2.2 2.5 2.8 3.1 Figure 26. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) K70 Sub-Family Data Sheet, Rev. 5, 10/2013. 60 Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors 0.18 0.16 0.14 CMP P Hystereris (V) 0.12 HYSTCTR Setting 0.1 00 01 0 08 0.08 10 11 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 Vin level (V) 1.9 2.2 2.5 2.8 3.1 Figure 27. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 6.6.3 12-bit DAC electrical characteristics 6.6.3.1 Symbol 12-bit DAC operating requirements Table 34. 12-bit DAC operating requirements Desciption Min. Max. Unit VDDA Supply voltage 1.71 3.
Peripheral operating requirements and behaviors 6.6.3.2 Symbol 12-bit DAC operating behaviors Table 35. 12-bit DAC operating behaviors Description IDDA_DACL Supply current — low-power mode Min. Typ. Max. Unit — — 150 μA — — 700 μA Notes P IDDA_DACH Supply current — high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) — low-power mode — 100 200 μs 1 tDACHP Full-scale settling time (0x080 to 0xF7F) — high-power mode — 15 30 μs 1 — 0.
Peripheral operating requirements and behaviors Figure 28. Typical INL error vs. digital code K70 Sub-Family Data Sheet, Rev. 5, 10/2013. Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors Figure 29. Offset at half scale vs. temperature 6.6.4 Voltage reference electrical specifications Table 36. VREF full-range operating requirements Symbol Description Min. Max. Unit VDDA Supply voltage 1.71 3.6 V TA Temperature CL Output load capacitance Operating temperature range of the device °C 100 nF Notes 1, 2 1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external reference.
Peripheral operating requirements and behaviors Table 37. VREF full-range operating behaviors Symbol Description Min. Typ. Max. Unit Notes Vout Voltage reference output with factory trim at nominal VDDA and temperature=25C 1.1915 1.195 1.1977 V 1 Vout Voltage reference output — factory trim 1.1584 — 1.2376 V 1 Vout Voltage reference output — user trim 1.193 — 1.197 V 1 Vstep Voltage reference trim step — 0.
Peripheral operating requirements and behaviors 6.8.1 Ethernet switching specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 6.8.1.1 MII signal switching specifications The following timing specs meet the requirements for MII style interfaces for a range of transceiver devices. Table 40. MII signal switching specifications Symbol — Description Min. RXCLK frequency Max.
Peripheral operating requirements and behaviors MII2 MII1 MII3 MII4 RXCLK (input) RXD[n:0] Valid data RXDV Valid data RXER Valid data Figure 31. RMII/MII receive signal timing diagram 6.8.1.2 RMII signal switching specifications The following timing specs meet the requirements for RMII style interfaces for a range of transceiver devices. Table 41. RMII signal switching specifications Num — Description EXTAL frequency (RMII input clock RMII_CLK) Min. Max.
Peripheral operating requirements and behaviors 6.8.3 USB DCD electrical specifications Table 42. USB DCD electrical specifications Symbol Description Min. Typ. Max. Unit VDP_SRC USB_DP source voltage (up to 250 μA) 0.5 — 0.7 V Threshold voltage for logic high 0.8 — 2.0 V 7 10 13 μA VLGC IDP_SRC USB_DP source current IDM_SINK USB_DM sink current 50 100 150 μA RDM_DWN D- pulldown resistance for data pin contact detect 14.25 — 24.8 kΩ VDAT_REF Data detect voltage 0.25 0.
Peripheral operating requirements and behaviors 6.8.5 ULPI timing specifications The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin Interface. Control and data timing requirements for the ULPI pins are given in the following table. These timings apply to synchronous mode only. All timings are measured with respect to the clock as seen at the USB_CLKIN pin. Table 44. ULPI timing specifications Num Description Min. Typ. Max.
Peripheral operating requirements and behaviors 6.8.6 CAN switching specifications See General switching specifications. 6.8.7 DSPI switching specifications (limited voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes.
Peripheral operating requirements and behaviors Table 46. Slave mode DSPI timing (limited voltage range) Num Description Operating voltage Min. Max. Unit 2.7 3.
Peripheral operating requirements and behaviors Table 47. Master mode DSPI timing (full voltage range) (continued) Num Description Min. Max. Unit Notes DS2 DSPI_SCK output high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) − 4 — ns 2 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) − 4 — ns 3 DS5 DSPI_SCK to DSPI_SOUT valid — 10 ns DS6 DSPI_SCK to DSPI_SOUT invalid -4.5 — ns DS7 DSPI_SIN to DSPI_SCK input setup 20.
Peripheral operating requirements and behaviors DSPI_SS DS10 DS9 DSPI_SCK DS15 (CPOL=0) DSPI_SOUT DS12 First data DS13 DSPI_SIN DS16 DS11 Last data Data DS14 First data Data Last data Figure 36. DSPI classic SPI timing — slave mode 6.8.9 Inter-Integrated Circuit Interface (I2C) timing Table 49. I 2C timing Characteristic Symbol Standard Mode Fast Mode Unit Minimum Maximum Minimum Maximum SCL Clock Frequency fSCL 0 100 0 400 kHz Hold time (repeated) START condition.
Peripheral operating requirements and behaviors 6. Cb = total capacitance of the one bus line in pF. SDA tf tLOW tSU; DAT tr tf tHD; STA tr tSP tBUF SCL S tHD; STA tHD; DAT tHIGH tSU; STA tSU; STO SR P S Figure 37. Timing definition for fast and standard mode devices on the I2C bus 6.8.10 UART switching specifications See General switching specifications. 6.8.
Peripheral operating requirements and behaviors Table 51. SDHC switching specifications over the full operating voltage range Num Symbol Description Min. Max. Unit Operating voltage 1.71 3.
Peripheral operating requirements and behaviors is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the frame sync (FS) signal shown in the following figures. 6.8.12.1 Normal Run, Wait and Stop mode performance over a limited operating voltage range This section provides the operating performance over a limited operating voltage for the device in Normal Run, Wait and Stop modes.
Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 39. I2S/SAI timing — master modes Table 53. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage range) Num. Characteristic Min. Max. Unit Operating voltage 2.7 3.
Peripheral operating requirements and behaviors S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 40. I2S/SAI timing — slave modes 6.8.12.2 Normal Run, Wait and Stop mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in Normal Run, Wait and Stop modes. Table 54.
Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 41. I2S/SAI timing — master modes Table 55. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.
Peripheral operating requirements and behaviors S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 42. I2S/SAI timing — slave modes 6.8.12.3 VLPR, VLPW, and VLPS mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in VLPR, VLPW, and VLPS modes. Table 56.
Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 43. I2S/SAI timing — master modes Table 57. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.
Peripheral operating requirements and behaviors S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 44. I2S/SAI timing — slave modes 6.9 Human-machine interfaces (HMI) 6.9.1 TSI electrical specifications Table 58. TSI electrical specifications Symbol Description Min. Typ. Max. Unit VDDTSI Operating voltage 1.71 — 3.
Peripheral operating requirements and behaviors 1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. 2. Fixed external capacitance of 20 pF. 3. REFCHRG = 2, EXTCHRG=0. 4. REFCHRG = 0, EXTCHRG = 10. 5. VDD = 3.0 V. 6. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current. 7.
Peripheral operating requirements and behaviors T1 GLCD_LSCLK GLCD_D[17:0] T2 T3 Figure 45. GLCD_LSCLK to GLCD_D[17:0] Timing Non-display region T1 GLCD_VSYNC T3 Display region T4 T2 GLCD_HSYNC GLCD_OE GLCD_D[17:0] Line Y Line Y Line 1 T5 T6 XMAX T7 GLCD_HSYNC GLCD_LSCLK GLCD_OE GLCD_D[15:0] (1,1) (1,2) (1,X) Figure 46. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing Table 60. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing Num Description Min. Max.
Peripheral operating requirements and behaviors NOTE • Ts is the GLCD_LSCLK period. GLCD_VSYNC, GLCD_HSYNC, and GLCD_OE can be programmed as active high or active low. In the preceding figure, all 3 signals are active low. GLCD_LSCLK can be programmed to be deactivated during the GLCD_VSYNC pulse or the GLCD_OE deasserted period. In the preceding figure, GLCD_LSCLK is always active. • XMAX is defined in number of pixels in one line.
Dimensions 7 Dimensions 7.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 256-pin MAPBGA 98ASA00346D 8 Pinout 8.1 Pins with active pull control after reset The following pins are actively pulled up or down after reset: Table 62.
Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 SDHC0_D0 ALT5 ALT6 ALT7 I2C1_SCL SPI1_SIN F2 PTE1/ LLWU_P0 ADC1_SE5a ADC1_SE5a PTE1/ LLWU_P0 SPI1_SOUT UART1_RX F3 PTE2/ LLWU_P1 ADC1_SE6a ADC1_SE6a PTE2/ LLWU_P1 SPI1_SCK UART1_CTS_b SDHC0_DCLK G2 PTE3 ADC1_SE7a ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_b SDHC0_CMD G7 VDD VDD VDD H7 VDDINT VDDINT VDDINT H8 VSS VSS VSS F1 PTF17 DISABLED PTF17 SPI2_SCK FTM0_CH4 UART0_RX G1 PTF18 DISABLED PTF18 SPI2_
Pinout 256 MAP BGA Pin Name Default ALT0 P1 PGA3_DP/ ADC3_DP0/ ADC2_DP3/ ADC1_DP1 PGA3_DP/ ADC3_DP0/ ADC2_DP3/ ADC1_DP1 PGA3_DP/ ADC3_DP0/ ADC2_DP3/ ADC1_DP1 P2 PGA3_DM/ ADC3_DM0/ ADC2_DM3/ ADC1_DM1 PGA3_DM/ ADC3_DM0/ ADC2_DM3/ ADC1_DM1 PGA3_DM/ ADC3_DM0/ ADC2_DM3/ ADC1_DM1 R1 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 R2 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 T1 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ A
Pinout 256 MAP BGA Pin Name Default ALT0 R6 TAMPER5 TAMPER5 TAMPER5 T6 XTAL32 XTAL32 XTAL32 T5 EXTAL32 EXTAL32 EXTAL32 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 P5 VBAT VBAT VBAT N6 TAMPER6 TAMPER6 TAMPER6 M6 TAMPER7 TAMPER7 TAMPER7 G9 VDD VDD VDD H10 VDDINT VDDINT VDDINT J8 VSS VSS VSS P7 PTE24 ADC0_SE17/ EXTAL1 ADC0_SE17/ EXTAL1 PTE24 CAN1_TX UART4_TX I2S1_TX_FS EWM_OUT_b I2S1_RXD1 R7 PTE25 ADC0_SE18/ XTAL1 ADC0_SE18/ XTAL1 PTE25 CAN1_RX UART4_RX I2
Pinout 256 MAP BGA R13 Pin Name PTA11 Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ADC3_SE15 ADC3_SE15 PTA11 ULPI_DATA1 FTM2_CH1 MII0_RXCLK FTM2_QD_ PHB M10 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 RMII0_RXD1/ MII0_RXD1 I2S0_TXD0 FTM1_QD_ PHA N10 PTA13/ LLWU_P4 CMP2_IN1 CMP2_IN1 PTA13/ LLWU_P4 CAN0_RX FTM1_CH1 RMII0_RXD0/ MII0_RXD0 I2S0_TX_FS FTM1_QD_ PHB R11 PTA14 CMP3_IN0 CMP3_IN0 PTA14 SPI0_PCS0 UART0_TX RMII0_CRS_ DV/ MII0_RXDV I2S0_RX_BCLK I2S0_TXD
Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 RMII0_MDC/ MII0_MDC ALT6 M11 PTB1 ADC0_SE9/ ADC1_SE9/ ADC2_SE9/ ADC3_SE9/ TSI0_CH6 ADC0_SE9/ ADC1_SE9/ ADC2_SE9/ ADC3_SE9/ TSI0_CH6 PTB1 I2C0_SDA FTM1_CH1 P15 PTB2 ADC0_SE12/ TSI0_CH7 ADC0_SE12/ TSI0_CH7 PTB2 I2C0_SCL UART0_RTS_b ENET0_1588_ TMR0 FTM0_FLT3 M14 PTB3 ADC0_SE13/ TSI0_CH8 ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDA UART0_CTS_ ENET0_1588_ b/ TMR1 UART0_COL_b FTM0_FLT0 N15 PTB4 ADC1_SE10 ADC1_SE10 PTB4 EN
Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 F14 PTC2 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 PTC2 SPI0_PCS2 UART1_CTS_b FTM0_CH1 FB_AD12/ NFC_DATA9 I2S0_TX_FS E13 PTC3/ LLWU_P7 CMP1_IN1 CMP1_IN1 PTC3/ LLWU_P7 SPI0_PCS1 UART1_RX FTM0_CH2 CLKOUT I2S0_TX_BCLK F15 PTF7 ADC2_SE7b ADC2_SE7b PTF7 FTM3_CH7 UART3_RX I2S1_TXD1 L9 VSS VSS VSS K10 VDD VDD VDD ALT7 F16 PTF8 DISABLED PTF8 FTM3_FLT0 UART3_TX I2S1_MCLK E14
Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 ALT2 PTD0/ LLWU_P12 ALT3 ALT4 ALT5 ALT6 SPI0_PCS0 UART2_RTS_b FTM3_CH0 FB_ALE/ FB_CS1_b/ FB_TS_b I2S1_RXD1 PTD1 SPI0_SCK UART2_CTS_b FTM3_CH1 FB_CS0_b I2S1_RXD0 L8 PTD0/ LLWU_P12 DISABLED F8 PTD1 ADC0_SE5b K6 PTD2/ LLWU_P13 DISABLED PTD2/ LLWU_P13 SPI0_SOUT UART2_RX FTM3_CH2 FB_AD4 I2S1_RX_FS J6 PTD3 DISABLED PTD3 SPI0_SIN UART2_TX FTM3_CH3 FB_AD3 I2S1_RX_BCLK K5 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI0_PCS1 UA
Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 B8 DDR_VDD DDR_VDD DDR_VDD A12 DDR_VSS DDR_VSS DDR_VSS C4 DDR_DQ13 DISABLED DDR_DQ13 B3 DDR_DQ14 DISABLED DDR_DQ14 A2 DDR_DQ15 DISABLED DDR_DQ15 A3 DDR_DM1 DISABLED DDR_DM1 E8 DDR_VSS DDR_VSS DDR_VSS B12 DDR_VDD DDR_VDD DDR_VDD A16 DDR_VSS DDR_VSS DDR_VSS C6 DDR_VREF DDR_VREF DDR_VREF C5 DDR_DQ0 DISABLED DDR_DQ0 B4 DDR_DQ1 DISABLED DDR_DQ1 A4 DDR_DQ2 DISABLED DDR_DQ2 C16 DDR_VDD DDR_VDD DDR_VDD C7 DDR
Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 D12 DDR_VSS DDR_VSS DDR_VSS C10 DDR_A4 DISABLED DDR_A4 A13 DDR_A5 DISABLED DDR_A5 A14 DDR_A6 DISABLED DDR_A6 D11 DDR_A7 DISABLED DDR_A7 A15 DDR_A8 DISABLED DDR_A8 E12 DDR_VDD DDR_VDD DDR_VDD E3 DDR_VSS DDR_VSS DDR_VSS B16 DDR_CKE DISABLED DDR_CKE B15 DDR_A9 DISABLED DDR_A9 B13 DDR_A10 DISABLED DDR_A10 B14 DDR_A11 DISABLED DDR_A11 C15 DDR_A12 DISABLED DDR_A12 D16 DDR_A13 DISABLED DDR_A13 D15 DDR_A14 D
Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 G4 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2 GLCD_D5 FTM3_CH0 H2 PTE6 DISABLED PTE6 SPI1_PCS3 UART3_CTS_b I2S0_MCLK GLCD_D6 FTM3_CH1 H1 PTF19 DISABLED PTF19 SPI2_SIN FTM1_CH1 UART5_RX GLCD_D15 H5 PTF20 DISABLED PTF20 SPI2_PCS1 FTM2_CH0 UART5_TX GLCD_D16 H3 PTE7 DISABLED PTE7 H4 PTE8 ADC2_SE16 ADC2_SE16 PTE8 J1 PTE9 ADC2_SE17 ADC2_SE17 PTE9 J2 PTE10 DISABLED K1 PTE11 ADC3_
Pinout 256 MAP BGA Pin Name Default ALT0 T1 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 T2 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 N5 VDDA VDDA VDDA P4 VREFH VREFH VREFH M4 VREFL VREFL VREFL N4 VSSA VSSA VSSA P3 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 N3 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ AD
Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT7 EWM_IN I2S1_TXD1 RTC_CLKOUT USB_CLKIN EzPort R7 PTE25 ADC0_SE18/ XTAL1 ADC0_SE18/ XTAL1 PTE25 CAN1_RX UART4_RX M7 PTE26 ADC3_SE5b ADC3_SE5b PTE26 ENET_1588_ CLKIN UART4_CTS_b I2S1_TXD0 GLCD_D15 K7 PTE27 ADC3_SE4b ADC3_SE4b PTE27 UART4_RTS_b I2S1_MCLK GLCD_D16 L7 PTE28 ADC3_SE7a ADC3_SE7a PTE28 T7 PTA0 JTAG_TCLK/ SWD_CLK/ EZP_CLK TSI0_CH1 PTA0 UART0_CTS_ FTM0_CH5 b/ UART0_COL_b JTAG_TCLK/ SW
Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 N11 PTA16 CMP3_IN2 CMP3_IN2 PTA16 SPI0_SOUT UART0_CTS_ RMII0_TXD0/ b/ MII0_TXD0 UART0_COL_b I2S0_RX_FS T11 PTA17 ADC1_SE17 ADC1_SE17 PTA17 SPI0_SIN UART0_RTS_b RMII0_TXD1/ MII0_TXD1 I2S0_MCLK P10 PTF23 ADC3_SE10 ADC3_SE10 PTF23 I2C0_SDA FTM1_CH1 TRACE_ CLKOUT GLCD_D19 R10 PTF24 ADC3_SE11 ADC3_SE11 PTF24 CAN1_RX FTM1_QD_ PHA TRACE_D3 GLCD_D20 R9 PTF25 ADC3_SE12 ADC3_SE12 PTF25 CAN1_TX
Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 M15 PTB5 ADC1_SE11 ADC1_SE11 PTB5 ENET0_1588_ TMR3 L14 PTB6 ADC1_SE12 ADC1_SE12 PTB6 FB_AD23 L15 PTB7 ADC1_SE13 ADC1_SE13 PTB7 FB_AD22 K14 PTB8 DISABLED PTB8 K15 PTB9 DISABLED PTB9 J13 PTB10 ADC1_SE14 ADC1_SE14 J14 PTB11 ADC1_SE15 ADC1_SE15 K9 VSS VSS VSS J10 VDD VDD VDD N16 ALT6 ALT7 FTM2_FLT0 UART3_RTS_b FB_AD21 SPI1_PCS1 UART3_CTS_b FB_AD20 PTB10 SPI1_PCS0 UART3_RX I2S1_TX_BCLK
Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 ALT2 PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ALT2 I2S0_RXD0 E15 PTC5/ LLWU_P9 DISABLED F12 PTC6/ LLWU_P10 CMP0_IN0 CMP0_IN0 PTC6/ LLWU_P10 SPI0_SOUT G12 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN H12 PTC8 ADC1_SE4b/ CMP0_IN2 ADC1_SE4b/ CMP0_IN2 F11 PTC9 ADC1_SE5b/ CMP0_IN3 G11 PTC10 H11 ALT3 ALT4 ALT5 ALT6 ALT7 FB_AD10/ NFC_DATA7 CMP0_OUT PDB0_EXTRG I2S0_RX_BCLK FB_AD9/ NFC_DATA6 I2S0_MCLK USB_SOF_ OUT I2S0_RX_FS FB_AD8/ NFC_DATA5
Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 J5 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_ FTM0_CH5 b/ UART0_COL_b FB_AD1/ NFC_DATA0 EWM_OUT_b K4 PTD6/ LLWU_P15 ADC0_SE7b ADC0_SE7b PTD6/ LLWU_P15 SPI0_PCS3 UART0_RX FB_AD0 FTM0_FLT0 H6 PTF13 DISABLED PTF13 UART2_RX GLCD_D9 G6 PTF14 DISABLED PTF14 UART2_TX GLCD_D10 T4 VSS VSS E7 PTD7 DISABLED PTD7 CMT_IRO UART0_TX J4 PTD8 DISABLED PTD8 I2C0_SCL UART5_RX FB_A16/ NFC_
Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 B12 DDR_VDD DDR_VDD DDR_VDD A16 DDR_VSS DDR_VSS DDR_VSS C6 DDR_VREF DDR_VREF DDR_VREF C5 DDR_DQ0 DISABLED DDR_DQ0 B4 DDR_DQ1 DISABLED DDR_DQ1 A4 DDR_DQ2 DISABLED DDR_DQ2 C16 DDR_VDD DDR_VDD DDR_VDD C7 DDR_VSS DDR_VSS DDR_VSS B6 DDR_DQ3 DISABLED DDR_DQ3 D6 DDR_DQ4 DISABLED DDR_DQ4 A6 DDR_DQ5 DISABLED DDR_DQ5 A7 DDR_ODT DISABLED DDR_ODT E11 DDR_VSS DDR_VSS DDR_VSS D2 DDR_VDD DDR_VDD DDR_VDD C9 DDR_VSS
Pinout 256 MAP BGA Pin Name Default ALT0 ALT1 E3 DDR_VSS DDR_VSS DDR_VSS B16 DDR_CKE DISABLED DDR_CKE B15 DDR_A9 DISABLED DDR_A9 B13 DDR_A10 DISABLED DDR_A10 B14 DDR_A11 DISABLED DDR_A11 C15 DDR_A12 DISABLED DDR_A12 D16 DDR_A13 DISABLED DDR_A13 D15 DDR_A14 DISABLED DDR_A14 E16 DDR_RAS_B DISABLED DDR_RAS_B C13 DDR_CAS_B DISABLED DDR_CAS_B D14 DDR_CS_B DISABLED DDR_CS_B D13 DDR_WE_B DISABLED DDR_WE_B ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort 8.
Revision History 1 2 4 3 5 6 7 8 9 10 11 12 13 14 15 16 A DDR_VSS DDR_DQ15 DDR_DM1 DDR_DQ2 DDR_VSS DDR_DQ5 DDR_ODT DDR_DQ7 DDR_BA0 DDR_CKB DDR_CK DDR_VSS DDR_A5 DDR_A6 DDR_A8 DDR_VSS A B DDR_VDD DDR_DQ11 DDR_DQ14 DDR_DQ1 DDR_VDD DDR_DQ3 DDR_DQ6 DDR_VDD DDR_BA2 DDR_BA1 DDR_A2 DDR_VDD DDR_A10 DDR_A11 DDR_A9 DDR_CKE B C DDR_DQ9 DDR_DQ10 DDR_DQ12 DDR_DQ13 DDR_DQ0 DDR_VREF DDR_VSS DDR_DQS0 DDR_VSS DDR_A4 DDR_A1 DDR_A3 DDR_CAS_B DDR_VSS DDR_A12 DDR_VDD C D DDR_DQ8 DD
Revision History Table 63. Revision History Rev. No. Date Substantial Changes 3 3/2012 Initial public release 4 10/2012 Replaced TBDs throughout. 5 10/2013 Changes for 4N96B mask set: • Min VDD operating requirement specification updated to support operation down to 1.71V. New specifications: • Updated Vdd_ddr min specification. • Added Vodpu specification. • Removed Ioz, Ioz_ddr, and Ioz_tamper Hi-Z leakage specfications. They have been replaced by new Iina, Iind, and Zind specifications.
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