Datasheet

1. For DDR1/DDR2, connect V
REF_DDR
to the same reference voltage used for the memory. For LPDDR1, connect V
REF_DDR
to the V
DD_DDR
voltage.
2. All 5 V tolerant digital I/O pins are internally clamped to V
SS
through an ESD protection diode. There is no diode
connection to V
DD
. If V
IN
is less than V
DIO_MIN
, a current limiting resistor is required. If V
IN
greater than V
DIO_MIN
(=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC injection
current limiting resistor is calculated as R=(V
DIO_MIN
-V
IN
)/|I
ICDIO
|.
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and
XTAL are analog pins.
4. All analog pins are internally clamped to V
SS
and V
DD
through ESD protection diodes. If V
IN
is less than V
AIO_MIN
or greater
than V
AIO_MAX
, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as
R=(V
AIO_MIN
-V
IN
)/|I
ICAIO
|. The positive injection current limiting resistor is calculated as R=(V
IN
-V
AIO_MAX
)/|I
ICAIO
|. Select the
larger of these two calculated resistances if the pin is exposed to positive and negative injection currents.
5. Open drain outputs must be pulled to VDD.
5.2.2 LVD and POR operating requirements
Table 2. LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
V
POR
Falling VDD POR detect voltage 0.8 1.1 1.5 V
V
LVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48 2.56 2.64 V
V
LVW1H
V
LVW2H
V
LVW3H
V
LVW4H
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
1
V
HYSH
Low-voltage inhibit reset/recover hysteresis —
high range
— ±80 — mV
V
LVDL
Falling low-voltage detect threshold — low range
(LVDV=00)
1.54 1.60 1.66 V
V
LVW1L
V
LVW2L
V
LVW3L
V
LVW4L
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
1
V
HYSL
Low-voltage inhibit reset/recover hysteresis —
low range
— ±60 — mV
V
BG
Bandgap voltage reference 0.97 1.00 1.03 V
t
LPO
Internal low power oscillator period
factory trimmed
900 1000 1100 μs
General
K70 Sub-Family Data Sheet, Rev. 5, 10/2013.
14 Freescale Semiconductor, Inc.