Datasheet

Table 4. Voltage and current operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
I
IND
Input leakage current, digital pins
• V
SS
≤ V
IN
≤ V
IL
• All digital pins
• V
IN
= V
DD
• All digital pins except PTD7
• PTD7
—
—
—
0.002
0.002
0.004
0.5
0.5
1
μA
μA
μA
2, 3
I
IND
Input leakage current, digital pins
• V
IL
< V
IN
< V
DD
• V
DD
= 3.6 V
• V
DD
= 3.0 V
• V
DD
= 2.5 V
• V
DD
= 1.7 V
—
—
—
—
18
12
8
3
26
19
13
6
μA
μA
μA
μA
2, 3, 4
I
IND
Input leakage current, digital pins
• V
DD
< V
IN
< 5.5 V — 1 50 μA
2, 3
Z
IND
Input impedance examples, digital pins
• V
DD
= 3.6 V
• V
DD
= 3.0 V
• V
DD
= 2.5 V
• V
DD
= 1.7 V
—
—
—
—
—
—
—
—
48
55
57
85
kΩ
kΩ
kΩ
kΩ
2, 5
I
IN_DDR
Input leakage current (per DDR pin) for full
temperature range
— — 1 μA
I
IN_DDR
Input leakage current (per DDR pin) at 25°C — — 0.025 μA
I
IN_Tamper
Input leakage current (per Tamper pin) for full
temperature range
— — 1 μA
I
IN_Tamper
Input leakage current (per Tamper pin) at 25°C — — 0.025 μA
R
PU
Internal pullup resistors (except Tamper pins) 20 — 50 kΩ 6
R
PD
Internal pulldown resistors (except Tamper pins) 20 — 50 kΩ 7
R
ODT
On-die termination (ODT) resistance for DDR2
• R
tt1(eff)
- 75 Ω
• R
tt2(eff)
- 150 Ω
60
120
—
—
90
180
Ω
Ω
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL.
3. Internal pull-up/pull-down resistors disabled.
4. Characterized, not tested in production.
5. Examples calculated using V
IL
relation, V
DD
, and max I
IND
: Z
IND
=V
IL
/I
IND
. This is the impedance needed to pull a high
signal to a level below V
IL
due to leakage when V
IL
< V
IN
< V
DD
. These examples assume signal source low = 0 V. See
Figure 2.
6. Measured at V
DD
supply voltage = V
DD
min and Vinput = V
SS
7. Measured at V
DD
supply voltage = V
DD
min and Vinput = V
DD
General
K70 Sub-Family Data Sheet, Rev. 5, 10/2013.
Freescale Semiconductor, Inc. 17