Datasheet

Figure 2. 5 V Tolerant Input IIND Parameter
5.2.4 Power mode transition operating behaviors
All specifications except t
POR
, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 150 MHz
• Bus clock = 75 MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
• MCG mode: FEI
Table 5. Power mode transition operating behaviors
Symbol Description Min. Max. Unit Notes
t
POR
After a POR event, amount of time from the point V
DD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
• V
DD
slew rate ≥ 5.7 kV/s
• V
DD
slew rate < 5.7 kV/s
—
—
300
1.7 V / (V
DD
slew rate)
μs
1
• VLLS1 → RUN
— 160 μs
• VLLS2 → RUN
— 114 μs
• VLLS3 → RUN
— 114 μs
• LLS → RUN
— 5.0 μs
• VLPS → RUN
— 5 μs
• STOP → RUN
— 4.8 μs
1. Normal boot (FTFE_FOPT[LPBOOT]=1)
General
K70 Sub-Family Data Sheet, Rev. 5, 10/2013.
18 Freescale Semiconductor, Inc.