Datasheet

Table 9. Device clock specifications (continued)
Symbol Description Min. Max. Unit Notes
f
SYS
System and core clock — 4 MHz
f
BUS
Bus clock — 4 MHz
FB_CLK FlexBus clock — 4 MHz
f
FLASH
Flash clock — 0.5 MHz
f
LPTMR
LPTMR clock — 4 MHz
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all pins configured for:
• GPIO signaling
• Other peripheral module signaling not explicitly stated elsewhere
Table 10. General switching specifications
Symbol Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5 — Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100 — ns 3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
16 — ns 3
External reset pulse width (digital glitch filter disabled) 100 — ns 3
Mode select (EZP_CS) hold time after reset
deassertion
2 — Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ V
DD
≤ 2.7V
• 2.7 ≤ V
DD
≤ 3.6V
• Slew enabled
• 1.71 ≤ V
DD
≤ 2.7V
• 2.7 ≤ V
DD
≤ 3.6V
—
—
—
—
14
8
36
24
ns
ns
ns
ns
4
Table continues on the next page...
General
K70 Sub-Family Data Sheet, Rev. 5, 10/2013.
24 Freescale Semiconductor, Inc.