Datasheet

Table 14. JTAG full voltage range electricals (continued)

Symbol Description Min. Max. Unit

J7 TCLK low to boundary scan output data valid — 25 ns

J8 TCLK low to boundary scan output high-Z — 25 ns

J9 TMS, TDI input data setup time to TCLK rise 8 — ns

J10 TMS, TDI input data hold time after TCLK rise 1.4 — ns

J11 TCLK low to TDO data valid — 22.1 ns

J12 TCLK low to TDO high-Z — 22.1 ns

J13 TRST assert time 100 — ns

J14 TRST setup time (negation) to TCLK high 8 — ns

J3 J3

J4 J4

TCLK (input)

Figure 7. Test clock input timing

Input data valid

Output data valid

TCLK

Data inputs

Data outputs

Figure 8. Boundary scan (JTAG) timing

Peripheral operating requirements and behaviors

K70 Sub-Family Data Sheet, Rev. 5, 10/2013.

30 Freescale Semiconductor, Inc.