Datasheet

Table 15. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
J
cyc_fll
FLL period jitter
• f
VCO
= 48 MHz
• f
VCO
= 98 MHz
—
—
180
150
—
—
ps
t
fll_acquire
FLL target frequency acquisition time — — 1 ms 6
PLL0,1
f
pll_ref
PLL reference frequency range 8 — 16 MHz
f
vcoclk_2x
VCO output frequency
180
—
360
MHz
f
vcoclk
PLL output frequency
90
—
180
MHz
f
vcoclk_90
PLL quadrature output frequency
90
—
180
MHz
I
pll
PLL0 operating current
• VCO @ 180 MHz (f
osc_hi_1
= 32 MHz, f
pll_ref
= 8 MHz, VDIV multiplier = 22)
— 2.8 — mA
7
I
pll
PLL0 operating current
• VCO @ 360 MHz (f
osc_hi_1
= 32 MHz, f
pll_ref
= 8 MHz, VDIV multiplier = 45)
— 4.7 — mA
7
I
pll
PLL1 operating current
• VCO @ 180 MHz (f
osc_hi_1
= 32 MHz, f
pll_ref
= 8 MHz, VDIV multiplier = 22)
— 2.3 — mA
7
I
pll
PLL1 operating current
• VCO @ 360 MHz (f
osc_hi_1
= 32 MHz, f
pll_ref
= 8 MHz, VDIV multiplier = 45)
— 3.6 — mA
7
t
pll_lock
Lock detector detection time — — 100 × 10
-6
+ 1075(1/
f
pll_ref
)
s 8
J
cyc_pll
PLL period jitter (RMS)
• f
vco
= 180 MHz
• f
vco
= 360 MHz
—
—
100
75
—
—
ps
ps
9
J
acc_pll
PLL accumulated jitter over 1µs (RMS)
• f
vco
= 180 MHz
• f
vco
= 360 MHz
—
—
600
300
—
—
ps
ps
10
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δf
dco_t
) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
Peripheral operating requirements and behaviors
K70 Sub-Family Data Sheet, Rev. 5, 10/2013.
Freescale Semiconductor, Inc. 33