Datasheet

tCS tCH
tWP
tDS tDH
data
data
data
tWC
tWH
NFC_CEn
NFC_WE
NFC_IOn
Figure 15. Write data latch cycle timing
tCH
tRP
data
data
data
tRC
tREH
tIS
tRR
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
Figure 16. Read data latch cycle timing in non-fast mode
tCH
tRP
data
data
data
tRC
tREH
tIS
tRR
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
Figure 17. Read data latch cycle timing in fast mode
6.4.4 DDR controller specifications
The following timing numbers must be followed to properly latch or drive data onto the
DDR memory bus. All timing numbers are relative to the DQS byte lanes.
Peripheral operating requirements and behaviors
K70 Sub-Family Data Sheet, Rev. 5, 10/2013.
Freescale Semiconductor, Inc. 45