Datasheet

Table 26. DDR controller — AC timing specifications
Symbol Description Min. Max. Unit Notes
Frequency of operation
• DDR1
• DDR2
• LPDDR
83.3
125
1
50
150
150
150
MHz
MHz
MHz
2
t
DDRCK
Clock period
• DDR1
• DDR2
• LPDDR
6.6
6.6
6.6
12
8
20
ns
ns
ns
V
OX-AC
DDRCK AC differential cross point voltage
• DDR1
• DDR2
• LPDDR
0.5 x V
DD_DDR
– 0.2 V
0.5 x V
DD_DDR
– 0.125 V
0.4 x V
DD_DDR
0.5 x V
DD_DDR
+ 0.2 V
0.5 x V
DD_DDR
+ 0.125 V
0.4 x V
DD_DDR
V
V
V
t
DDRCKH
Pulse width high 0.45 0.55 t
DDRCK
3
t
DDRCKL
Pulse width low 0.45 0.55 t
DDRCK
3
t
CMV
Address, DDR_CKE, DDR_CAS, DDR_RAS,
DDR_WE, DDR_CSn — output setup
0.5 x t
DDRCK
–
1
— ns 4
t
CMH
Address, DDR_CKE, DDR_CAS, DDR_RAS,
DDR_WE, DDR_CSn — output hold
0.5 x t
DDRCK
–
1
— ns
t
DQSS
DQS rising edge to CK rising edge -0.2 x t
DDRCK
0.2 x t
DDRCK
ns
t
QS
Data and data mask output setup (DQ→DQS)
relative to DQS (DDR write mode)
0.25 x t
DDRCK
–
1
— ns 5, 6
t
QH
Data and data mask output hold (DQS→DQ)
relative to DQS (DDR write mode)
0.25 x t
DDRCK
–
1
— ns 7
t
DQSQ
DQS-DQ skew for DQS and associated DQ
signals
– (0.25 x
t
DDRCK
– 1)
0.25 x t
DDRCK
–
1
ns 8
1. This is minimum frequency of operation according to JEDEC DDR2 specification.
2. DDR data rate = 2 x DDR clock frequency
3. Pulse width high plus pulse width low cannot exceed min and max clock period.
4. Command output setup should be 1/2 the memory bus clock (t
DDRCK
) plus some minor adjustments for process,
temperature, and voltage variations.
5. This specification relates to the required input setup time of DDR memories. The microprocessor's output setup should be
larger than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation.
DDR_DQ[15:8] is relative to DDR_DQS[1]; DDR_DQ[7:0] is relative to DDR_DQS[0].
6. The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats
are valid for each subsequent DQS edge.
7. This specification relates to the required hold time of DDR memories. DDR_DQ[15:8] is relative to DDR_DQS[1];
DDR_DQ[7:0] is relative to DDR_DQS[0]
8. Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or
other factors).
Peripheral operating requirements and behaviors
K70 Sub-Family Data Sheet, Rev. 5, 10/2013.
46 Freescale Semiconductor, Inc.