Datasheet

1 2 3 4 5 6 7 8 9 10
CMD CMD
COLROW
WD1
WD2 WD3 WD4
tDDRCK
tDDRCKH
tDDRCKL
tCMV
tCMH
tQH
tQS
tDQSS
DDR_CLK
DDR__CLK
DDR_CSn, DDR_WE
DDR_CAS, DDR_RAS
DDR_An
DDR_DQSn
DDR_DMn
DDR_DQn
Figure 18. DDR write timing
1 2 3 4 5 6 7 8 9 10 11 12
CMD
ROW
COL
RD1 RD2
RD3RD4
RD1
RD2RD3RD4
CMD
DQS read preamble
DQS read preamble
tDDRCK
tDDRCHH
tDDRCKL
CL=3.0
tCMV
CL=2.5
tCMH
DDR_CLK
DDR__CLK
DDR_CSn, DDR_WE
DDR_CAS, DDR_RAS
DDR_An
DDR_DQS (CL=2.5)
DDR_DQn (CL=2.5)
DDR_DQS (CL=3.0)
DDR_DQn (CL=3.0)
RD3 RD4
RD1 RD2
RD3
RD4
Figure 19. DDR read timing
Peripheral operating requirements and behaviors
K70 Sub-Family Data Sheet, Rev. 5, 10/2013.
Freescale Semiconductor, Inc. 47