Datasheet

Table 32. 16-bit ADC with PGA characteristics (continued)
Symbol Description Conditions Min. Typ.
1
Max. Unit Notes
G Gain
4
• PGAG=0
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6
0.95
1.9
3.8
7.6
15.2
30.0
58.8
1
2
4
8
16
31.6
63.3
1.05
2.1
4.2
8.4
16.6
33.2
67.8
R
AS
< 100Ω
BW Input signal
bandwidth
• 16-bit modes
• < 16-bit modes
—
—
—
—
4
40
kHz
kHz
PSRR Power supply
rejection ratio
Gain=1 — -84 — dB V
DDA
= 3V
±100mV,
f
VDDA
= 50Hz,
60Hz
CMRR Common mode
rejection ratio
• Gain=1
• Gain=64
—
—
-84
-85
—
—
dB
dB
V
CM
=
500mVpp,
f
VCM
= 50Hz,
100Hz
V
OFS
Input offset
voltage
• Chopping disabled
(ADC_PGA[PGACHPb]
=1)
• Chopping enabled
(ADC_PGA[PGACHPb]
=0)
—
—
2.4
0.2
—
—
mV
mV
Output offset =
V
OFS
*(Gain+1)
T
GSW
Gain switching
settling time
— — 10 µs 5
dG/dT Gain drift over full
temperature range
• Gain=1
• Gain=64
—
—
6
31
10
42
ppm/°C
ppm/°C
dG/dV
DDA
Gain drift over
supply voltage
• Gain=1
• Gain=64
—
—
0.07
0.14
0.21
0.31
%/V
%/V
V
DDA
from 1.71
to 3.6V
E
IL
Input leakage
error
All modes I
In
× R
AS
mV I
In
= leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
V
PP,DIFF
Maximum
differential input
signal swing
where V
X
= V
REFPGA
× 0.583
V 6
SNR Signal-to-noise
ratio
• Gain=1
• Gain=64
80
52
90
66
—
—
dB
dB
16-bit
differential
mode,
Average=32
Table continues on the next page...
Peripheral operating requirements and behaviors
K70 Sub-Family Data Sheet, Rev. 5, 10/2013.
Freescale Semiconductor, Inc. 57