Datasheet

1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
2. Fixed external capacitance of 20 pF.
3. REFCHRG = 2, EXTCHRG=0.
4. REFCHRG = 0, EXTCHRG = 10.
5. V
DD
= 3.0 V.
6. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
7. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current.
8. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
10. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
11. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes. Sensitivity
depends on the configuration used. The documented values are provided as examples calculated for a specific
configuration of operating conditions using the following equation: (C
ref
* I
ext
)/( I
ref
* PS * NSCN)
The typical value is calculated with the following configuration:
I
ext
= 6 μA (EXTCHRG = 2), PS = 128, NSCN = 2, I
ref
= 16 μA (REFCHRG = 7), C
ref
= 1.0 pF
The minimum value is calculated with the following configuration:
I
ext
= 2 μA (EXTCHRG = 0), PS = 128, NSCN = 32, I
ref
= 32 μA (REFCHRG = 15), C
ref
= 0.5 pF
The highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be
measured by a single count.
12. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, EXTCHRG = 7.
13. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of
20 pF. Data is captured with an average of 7 periods window.
6.9.2 LCDC electrical specifications
Table 59. GLCD_LSCLK Timing
Num Description Min. Max. Unit
T1 GLCD_LSCLK Period 25 2000 ns
T2 Pixel data setup time 8 — ns
T3 Pixel data up time 8 — ns
NOTE
The pixel clock is equal to GLCD_LSCLK / (PCD + 1). When
it is in CSTN, TFT, or monochrome mode with bus width = 1,
GLCD_LSCLK is equal to the pixel clock. When it is in
monochrome with other bus width settings, GLCD_LSCLK is
equal to the pixel clock divided by bus width. The polarity of
GLCD_LSCLK and GLCD_D signals can also be programmed.
Peripheral operating requirements and behaviors
K70 Sub-Family Data Sheet, Rev. 5, 10/2013.
Freescale Semiconductor, Inc. 83