Datasheet

GLCD_D[17:0]
GLCD_LSCLK
T1
T3
T2
Figure 45. GLCD_LSCLK to GLCD_D[17:0] Timing
GLCD_VSYNC
GLCD_HSYNC
GLCD_OE
GLCD_D[17:0]
T2
T1
Non-display region
T4T3
Display region
Line
Y
Line
Y
Line
1
(1,1)
T7XMAXT6T5
GLCD_HSYNC
GLCD_LSCLK
GLCD_OE
GLCD_D[15:0]
(1,2) (1,X)
Figure 46. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing
Table 60. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing
Num Description Min. Max. Unit
T1 End of GLCD_OE to beginning of GLCD_VSYNC T5 + T6 + T7
– 1
(VWAIT1 ×
T2) + T5 + T6
+ T7 – 1
Ts
T2 GLCD_HSYNC period — XMAX + T5 +
T6 + T7
Ts
T3 GLCD_VSYNC pulse width T2 VWIDTH × T2 Ts
T4 End of GLCD_VSYNC to beginning of GLCD_OE 1 (VWAIT2 ×
T2) + 1
Ts
T5 GLCD_HSYNC pulse width 1 HWIDTH + 1 Ts
T6 End of GLCD_HSYNC to beginning to GLCD_OE 3 HWAIT2 + 3 Ts
T7 End of GLCD_OE to beginning of GLCD_HSYNC 1 HWAIT1 + 1 Ts
Peripheral operating requirements and behaviors
K70 Sub-Family Data Sheet, Rev. 5, 10/2013.
84 Freescale Semiconductor, Inc.