Datasheet

NOTE
• Ts is the GLCD_LSCLK period. GLCD_VSYNC,
GLCD_HSYNC, and GLCD_OE can be programmed as
active high or active low. In the preceding figure, all 3
signals are active low. GLCD_LSCLK can be programmed
to be deactivated during the GLCD_VSYNC pulse or the
GLCD_OE deasserted period. In the preceding figure,
GLCD_LSCLK is always active.
• XMAX is defined in number of pixels in one line.
GLCD_LSCLK
GLCD_D[15:0]
GLCD_HSYNC
T2
T1
T2T3 XMAX T4
TS
GLCD_VSYNC
T1
Figure 47. Non-TFT Mode Panel Timing
Table 61. Non-TFT Mode Panel Timing
Num Description Min. Max. Unit
T1 GLCD_HSYNC to GLCD_VSYNC delay 2 HWAIT2 + 2 Tpix
T2 GLCD_HSYNC pulse width 1 HWIDTH + 1 Tpix
T3 GLCD_VSYNC to GLCD_LSCLK — 0 ≤ T3 ≤ Ts —
T4 GLCD_LSCLK to GLCD_HSYNC 1 HWAIT1 + 1 Tpix
NOTE
Ts is the GLCD_LSCLK period while Tpix is the pixel clock
period. GLCD_VSYNC, GLCD_HSYNC, and GLCD_LSCLK
can be programmed as active high or active low. In the
preceding figure, all these 3 signals are active high. When it is
in CSTN mode or monochrome mode with bus width = 1, T3 =
Tpix = Ts. When it is in monochrome mode with bus width = 2,
4 and 8, T3 = 1, 2 and 4 Tpix respectively.
Peripheral operating requirements and behaviors
K70 Sub-Family Data Sheet, Rev. 5, 10/2013.
Freescale Semiconductor, Inc. 85