Datasheet

256
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
D12 DDR_VSS DDR_VSS DDR_VSS
C10 DDR_A4 DISABLED DDR_A4
A13 DDR_A5 DISABLED DDR_A5
A14 DDR_A6 DISABLED DDR_A6
D11 DDR_A7 DISABLED DDR_A7
A15 DDR_A8 DISABLED DDR_A8
E12 DDR_VDD DDR_VDD DDR_VDD
E3 DDR_VSS DDR_VSS DDR_VSS
B16 DDR_CKE DISABLED DDR_CKE
B15 DDR_A9 DISABLED DDR_A9
B13 DDR_A10 DISABLED DDR_A10
B14 DDR_A11 DISABLED DDR_A11
C15 DDR_A12 DISABLED DDR_A12
D16 DDR_A13 DISABLED DDR_A13
D15 DDR_A14 DISABLED DDR_A14
E16 DDR_RAS_B DISABLED DDR_RAS_B
C13 DDR_CAS_B DISABLED DDR_CAS_B
D14 DDR_CS_B DISABLED DDR_CS_B
D13 DDR_WE_B DISABLED DDR_WE_B
8.3 K70 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
256
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
E2 PTE0 ADC1_SE4a ADC1_SE4a PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 GLCD_D0 I2C1_SDA RTC_CLKOUT
F2 PTE1/
LLWU_P0
ADC1_SE5a ADC1_SE5a PTE1/
LLWU_P0
SPI1_SOUT UART1_RX SDHC0_D0 GLCD_D1 I2C1_SCL SPI1_SIN
F3 PTE2/
LLWU_P1
ADC1_SE6a ADC1_SE6a PTE2/
LLWU_P1
SPI1_SCK UART1_CTS_b SDHC0_DCLK GLCD_D2
G2 PTE3 ADC1_SE7a ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_b SDHC0_CMD GLCD_D3 SPI1_SOUT
G7 VDD VDD VDD
H7 VDDINT VDDINT VDDINT
H8 VSS VSS VSS
F1 PTF17 DISABLED PTF17 SPI2_SCK FTM0_CH4 UART0_RX GLCD_D13
G1 PTF18 DISABLED PTF18 SPI2_SOUT FTM1_CH0 UART0_TX GLCD_D14
G3 PTE4/
LLWU_P2
DISABLED PTE4/
LLWU_P2
SPI1_PCS0 UART3_TX SDHC0_D3 GLCD_D4
Pinout
K70 Sub-Family Data Sheet, Rev. 5, 10/2013.
Freescale Semiconductor, Inc. 95