Datasheet

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Kinetis KL05 32 KB Flash

48 MHz Cortex-M0+ Based Microcontroller

Designed with efficiency in mind. Features a size efficient, small

package, energy efficient ARM Cortex-M0+ 32-bit performance.

Shares the comprehensive enablement and scalability of the

Kinetis family.

This product offers:

• Run power consumption down to 45 μA/MHz in very low

power run mode

• Static power consumption down to 2 μA with full state

retention and 4 μs wakeup

• Ultra-efficient Cortex-M0+ processor running up to 48MHz

with industry leading throughput

• Memory option is up to 32 KB Flash and 4 KB RAM

• Energy-saving architecture is optimized for low power with

90 nm TFS technology, clock and power gating techniques,

and zero wait state flash memory controller

Performance

• 48 MHz ARM

Cortex

-M0+ core

Memories and memory interfaces

• Up to 32 KB program flash memory

• Up to 4 KB SRAM

System peripherals

• Nine low-power modes to provide power optimization

based on application requirements

• COP Software watchdog

• 4-channel DMA controller, supporting up to 63 request

sources

• Low-leakage wakeup unit

• SWD debug interface and Micro Trace Buffer

• Bit Manipulation Engine

Clocks

• 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator

• Multi-purpose clock source

• 1 kHz LPO clock

Operating Characteristics

• Voltage range: 1.71 to 3.6 V

• Flash write voltage range: 1.71 to 3.6 V

• Temperature range (ambient): -40 to 105°C

Human-machine interface

• Low-power hardware touch sensor interface (TSI)

• Up to 41 general-purpose input/output (GPIO)

Communication interfaces

• One 8-bit SPI module

• One low power UART module

• One I2C module

Analog Modules

• 12-bit SAR ADC

• 12-bit DAC

• Analog comparator (CMP) containing a 6-bit DAC

and programmable reference input

Timers

• Six channel Timer/PWM (TPM)

• One 2-channel Timer/PWM module

• Periodic interrupt timers

• 16-bit low-power timer (LPTMR)

• Real time clock

Security and integrity modules

• 80-bit unique identification number per chip

MKL05ZxxVFK4

MKL05ZxxVLC4

MKL05ZxxVFM4

MKL05ZxxVLF4

24-pin QFN (FK)

4 x 4 x 1 Pitch 0.5 mm

32-pin QFN (FM)

5 x 5 x 1 Pitch 0.5 mm

32-pin LQFP (LC)

7 x 7 x 1.4 Pitch 0.8

48-pin LQFP (LF)

7 x 7 x 1.4 Pitch 0.5

Freescale Semiconductor, Inc.

KL05P48M48SF1

Data Sheet: Technical Data Rev 4 03/2014

Freescale reserves the right to change the detail specifications as may be required to

Summary of content (53 pages)

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Freescale Semiconductor, Inc. Data Sheet: Technical Data KL05P48M48SF1 Rev 4 03/2014 Kinetis KL05 32 KB Flash 48 MHz Cortex-M0+ Based Microcontroller Designed with efficiency in mind. Features a size efficient, small package, energy efficient ARM Cortex-M0+ 32-bit performance. Shares the comprehensive enablement and scalability of the Kinetis family.
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Ordering Information Part Number Memory Maximum number of I\O's Flash (KB) SRAM (KB) MKL05Z8VFK4 8 1 22 MKL05Z16VFK4 16 2 22 MKL05Z32VFK4 32 4 22 MKL05Z8VLC4 8 1 28 MKL05Z16VLC4 16 2 28 MKL05Z32VLC4 32 4 28 MKL05Z8VFM4 8 1 28 MKL05Z16VFM4 16 2 28 MKL05Z32VFM4 32 4 28 MKL05Z16VLF4 16 2 41 MKL05Z32VLF4 32 4 41 Related Resources Type Description Selector Guide The Freescale Solution Advisor is a web-based tool that features interactive application wizards and
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Table of Contents 1 Ratings..................................................................................4 1.1 Thermal handling ratings...............................................4 1.2 Moisture handling ratings...............................................4 1.3 ESD handling ratings.....................................................4 1.4 Voltage and current operating ratings............................4 2 General.................................................................................5 2.
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Ratings 1 Ratings 1.1 Thermal handling ratings Table 1. Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.2 Moisture handling ratings Table 2.
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General 1.4 Voltage and current operating ratings Table 4. Voltage and current operating ratings Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V IDD Digital supply current — 120 mA VIO IO pin input voltage –0.3 VDD + 0.3 V Instantaneous maximum current single pin limit (applies to all port pins) –25 25 mA VDD – 0.3 VDD + 0.3 V ID VDDA Analog supply voltage 2 General 2.
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General 2.2.1 Voltage and current operating requirements Table 5. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V — VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V — VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V — VIH VIL Input high voltage — • 2.7 V ≤ VDD ≤ 3.6 V 0.7 × VDD — V • 1.7 V ≤ VDD ≤ 2.7 V 0.75 × VDD — V Input low voltage — • 2.7 V ≤ VDD ≤ 3.
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General Table 6. VDD supply LVD and POR operating requirements (continued) Symbol Min. Typ. Max. Unit VLVW1H Description • Level 1 falling (LVWV = 00) 2.62 2.70 2.78 V VLVW2H • Level 2 falling (LVWV = 01) 2.72 2.80 2.88 V VLVW3H • Level 3 falling (LVWV = 10) 2.82 2.90 2.98 V VLVW4H • Level 4 falling (LVWV = 11) 2.92 3.00 3.08 V — ±60 — mV — 1.54 1.60 1.
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General Table 7. Voltage and current operating behaviors (continued) Symbol VOL Description Min. Max. Unit Notes Output low voltage — High drive pad 1 • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA — • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA 0.5 V — 0.5 V Output low current total for all ports — 100 mA IIN Input leakage current (per pin) for full temperature range — 1 μA 3 IIN Input leakage current (per pin) at 25 °C — 0.
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General Table 8. Power mode transition operating behaviors (continued) Symbol Description Min. Typ. Max. Unit — 93 115 μs — 42 53 μs — 4 4.6 μs — 4 4.4 μs — 4 4.4 μs • VLLS3 → RUN • LLS → RUN • VLPS → RUN • STOP → RUN 1. Normal boot (FTFA_FOPT[LPBOOT]=11). 2.2.5 Power consumption operating behaviors The maximum values stated in the following table represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). Table 9.
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General Table 9. Power consumption operating behaviors (continued) Symbol Description Min. IDD_WAIT Wait mode current - core disabled / 24 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled • at 3.0 V IDD_PSTOP2 Stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 MHz bus / flash disabled (flash doze enabled) • at 3.0 V IDD_VLPRCO Very-low-power run mode current in compute operation - 4 MHz core / 0.
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General Table 9. Power consumption operating behaviors (continued) Symbol Min. Typ. Max.1 Unit • at 25 °C — 1.72 2.01 μA • at 50 °C — 2.52 3.18 • at 70 °C — 4.32 5.94 • at 85 °C — 7.18 10.00 • at 105 °C — 18.67 25.65 — 1.16 1.36 — 1.78 2.27 — 3.23 4.38 — 5.57 7.53 — 14.80 19.74 — 0.64 0.81 — 1.14 1.50 — 2.35 3.20 — 4.37 5.80 — 12.40 16.13 — 0.38 0.54 — 0.88 1.23 — 2.10 2.95 — 4.14 5.59 — 12.00 15.
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General 2. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 3. MCG configured for FEI mode. 4. Incremental current consumption from peripheral activity is not included. 5. MCG configured for BLPI mode. 6. No brownout Table 10.
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General Table 10. Low power mode peripheral adders — typical value (continued) Symbol ITPM Description TPM peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source configured for output compare generating 100 Hz clock signal. No load is placed on the I/O generating the clock signal. Includes selected clock source and I/O switching currents.
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General Run Mode Current VS Core Frequency Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE 7.00E-03 6.00E-03 Current Consumption on VDD (A) 5.00E-03 4.00E-03 All Peripheral CLK Gates All Off All On 3.00E-03 2.00E-03 1.00E-03 000.00E+00 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-2 1 2 3 4 6 12 24 48 CLK Ratio Flash-Core Core Freq (MHz) Figure 2. Run mode supply current vs. core frequency 14 Freescale Semiconductor, Inc.
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General VLPR Mode Current VS Core Frequency Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE 350.00E-06 300.00E-06 Current Consumption on VDD (A) 250.00E-06 200.00E-06 All Peripheral CLK Gates All Off All On 150.00E-06 100.00E-06 50.00E-06 000.00E+00 '1-1 '1-2 1 '1-2 '1-4 2 4 CLK Ratio Flash-Core Core Freq (MHz) Figure 3. VLPR mode current vs. core frequency 2.2.
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General • AN2764: Improving the Transient Immunity Performance of MicrocontrollerBased Applications • AN1259: System Design and Layout Techniques for Noise Reduction in MCUBased Systems 2.2.7 Capacitance attributes Table 11. Capacitance attributes Symbol CIN Description Input capacitance Min. Max. Unit — 7 pF Min. Max. Unit 2.3 Switching specifications 2.3.1 Device clock specifications Table 12.
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General 2.3.2 General switching specifications These general-purpose specifications apply to all signals configured for GPIO and UART signals. Table 13. General switching specifications Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path 1.
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Peripheral operating requirements and behaviors Table 15. Thermal attributes (continued) Board type Symbol Single-layer (1S) RθJMA Four-layer (2s2p) Description 48 LQFP 32 LQFP 32 QFN 24 QFN Unit Notes Thermal resistance, junction to ambient (200 ft./min. air speed) 70 74 81 92 °C/W RθJMA Thermal resistance, junction to ambient (200 ft./min.
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Peripheral operating requirements and behaviors Table 16. SWD full voltage range electricals (continued) Symbol Description Min. Max. Unit 20 — ns • Serial wire debug J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns J11 SWD_CLK high to SWD_DIO data valid — 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns J2 J3 J3 SWD_CLK (input) J4 J4 Figure 4.
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Peripheral operating requirements and behaviors 3.2 System modules There are no specifications necessary for the device's system modules. 3.3 Clock modules 3.3.1 MCG specifications Table 17. MCG specifications Symbol Description Min. Typ. Max. Unit Notes fints_ft Internal reference frequency (slow clock) — factory trimmed at nominal VDD and 25 °C — 32.768 — kHz fints_t Internal reference frequency (slow clock) — user trimmed 31.25 — 39.0625 kHz — ± 0.3 ± 0.
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Peripheral operating requirements and behaviors Table 17. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit Notes — 180 — ps 7 — — 1 ms 8 1464 × ffll_ref Jcyc_fll FLL period jitter • fVCO = 48 MHz tfll_acquire FLL target frequency acquisition time 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2.
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Peripheral operating requirements and behaviors Table 18. Oscillator DC electrical specifications (continued) Symbol Description Min. Typ. Max.
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Peripheral operating requirements and behaviors 3.3.2.2 Symbol Oscillator frequency specifications Table 19. Oscillator frequency specifications Min. Typ. Max.
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Peripheral operating requirements and behaviors Table 20. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit thvpgm4 Notes Longword Program high-voltage time — 7.5 18 μs thversscr Sector Erase high-voltage time — 13 113 ms 1 thversall Erase All high-voltage time — 52 452 ms 1 1. Maximum time based on expectations at cycling end-of-life. 3.4.1.2 Flash timing specifications — commands Table 21.
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Peripheral operating requirements and behaviors Table 23. NVM reliability specifications (continued) Min. Typ.1 Max. Unit tnvmretp10k Data retention after up to 10 K cycles 5 50 — years tnvmretp1k Data retention after up to 1 K cycles 20 100 — years nnvmcycp Cycling endurance 10 K 50 K — cycles Symbol Description Notes 2 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 °C use profile.
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Peripheral operating requirements and behaviors Table 24. 12-bit ADC operating conditions (continued) Symbol Description Conditions RAS Analog source resistance (external) 12-bit modes Min. Typ.1 Max. Unit Notes 4 fADCK < 4 MHz — — 5 kΩ fADCK ADC conversion ≤ 12-bit mode clock frequency 1.0 — 18.0 MHz Crate ADC conversion ≤ 12-bit modes rate No ADC hardware averaging 5 6 20.000 — 818.330 Ksps Continuous conversions enabled, subsequent conversion time 1.
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Peripheral operating requirements and behaviors 3.6.1.2 12-bit ADC electrical characteristics Table 25. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description IDDA_ADC Supply current ADC asynchronous clock source fADACK Conditions1 • ADLPC = 1, ADHSC = 0 • ADLPC = 1, ADHSC = 1 • ADLPC = 0, ADHSC = 0 Min. Typ.2 Max. Unit Notes 0.215 — 1.7 mA 3 1.2 2.4 3.9 MHz 2.4 4.0 6.1 MHz tADACK = 1/ fADACK 3.0 5.2 7.3 MHz 4.4 6.2 9.
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Peripheral operating requirements and behaviors 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. ADC conversion clock < 3 MHz Figure 7. Typical ENOB vs. ADC_CLK for 12-bit single-ended mode 3.
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Peripheral operating requirements and behaviors Table 26. Comparator and 6-bit DAC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit • CR0[HYSTCTR] = 10 — 20 — mV • CR0[HYSTCTR] = 11 — 30 — mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.
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Peripheral operating requirements and behaviors CMP Hysteresis vs Vinn 180.00E-03 160.00E-03 140.00E-03 CMP Hysteresis (V) 120.00E-03 HYSTCTR Setting 100.00E-03 0 1 80.00E-03 2 3 60.00E-03 40.00E-03 20.00E-03 000.00E+00 0.1 0.4 0.7 1 -20.00E-03 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vinn (V) Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 3.6.3 12-bit DAC electrical characteristics 3.6.3.1 Symbol 12-bit DAC operating requirements Table 27.
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Peripheral operating requirements and behaviors Table 28. 12-bit DAC operating behaviors (continued) Symbol Description tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) — low-power mode and high-speed mode Min. Typ. Max. Unit Notes — 0.
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Peripheral operating requirements and behaviors 8 6 4 DAC12 INL (LSB) 2 0 -2 -4 -6 -8 0 500 1000 1500 2000 2500 3000 3500 4000 Digital Code Figure 10. Typical INL error vs. digital code 32 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014.
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Peripheral operating requirements and behaviors 1.499 DAC12 Mid Level Code Voltage 1.4985 1.498 1.4975 1.497 1.4965 1.496 -40 55 25 85 105 125 Temperature °C Figure 11. Offset at half scale vs. temperature 3.7 Timers See General switching specifications. 3.8 Communication interfaces Kinetis KL05 32 KB Flash, Rev4 03/2014. 33 Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors 3.8.1 SPI switching specifications The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. See the SPI chapter of the chip's Reference Manual for information about the modified transfer formats used for communicating with slower peripheral devices.
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Peripheral operating requirements and behaviors Table 30. SPI master mode timing on slew rate enabled pads (continued) Num. Symbol 8 tv 9 Description Min. Max. Unit Note Data valid (after SPSCK edge) — 52 ns — tHO Data hold time (outputs) 0 — ns — 10 tRI Rise time input — tperiph – 25 ns — tFI Fall time input 11 tRO Rise time output — 36 ns — tFO Fall time output 1. For SPI0, fperiph is the bus clock (fBUS). 2.
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Peripheral operating requirements and behaviors SS 1 (OUTPUT) 2 3 10 11 4 10 11 SPSCK (CPOL=0) (OUTPUT) 5 SPSCK (CPOL=1) (OUTPUT) 5 6 MISO (INPUT) 7 MSB IN BIT 6 . . . 1 2 9 8 MOSI (OUTPUT) LSB IN PORT DATA MASTER MSB OUT 2 BIT 6 . . . 1 PORT DATA MASTER LSB OUT 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 13. SPI master mode timing (CPHA = 1) Table 31. SPI slave mode timing on slew rate disabled pads Num.
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Peripheral operating requirements and behaviors Table 32. SPI slave mode timing on slew rate enabled pads Num. Symbol 1 fop 2 tSPSCK 3 tLead Enable lead time 4 tLag Enable lag time 5 tWSPSCK 6 tSU 7 Frequency of operation SPSCK period Min. Max.
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Peripheral operating requirements and behaviors SS (INPUT) 4 2 3 SPSCK (CPOL=0) (INPUT) 5 SPSCK (CPOL=1) (INPUT) 5 see note SLAVE 8 MSB OUT 6 MOSI (INPUT) 13 12 13 11 10 MISO (OUTPUT) 12 9 BIT 6 . . . 1 SLAVE LSB OUT BIT 6 . . . 1 LSB IN 7 MSB IN NOTE: Not defined Figure 15. SPI slave mode timing (CPHA = 1) 3.8.2 Inter-Integrated Circuit Interface (I2C) timing Table 33.
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Peripheral operating requirements and behaviors 2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 4. Input signal Slew = 10 ns and Output Load = 50 pF 5.
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Dimensions 4 Dimensions 4.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 24-pin QFN 98ASA00474D 32-pin QFN 98ASA00473D 32-pin LQFP 98ASH70029A 48-pin LQFP 98ASH00962A 5 Pinout 5.
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Pinout 48 LQFP 32 QFN 32 LQFP 24 QFN Pin Name Default 9 7 7 5 PTA3 EXTAL0 EXTAL0 PTA3 I2C0_SCL I2C0_SDA 10 8 8 6 PTA4/ LLWU_P0 XTAL0 XTAL0 PTA4/ LLWU_P0 I2C0_SDA I2C0_SCL 11 — — — VSS VSS VSS 12 — — — PTB18 DISABLED DISABLED PTB18 13 — — — PTB19 DISABLED DISABLED PTB19 14 9 9 7 PTA5/ LLWU_P1/ RTC_CLK_IN DISABLED DISABLED PTA5/ LLWU_P1/ RTC_CLK_IN TPM0_CH5 SPI0_SS_b 15 10 10 8 PTA6/ LLWU_P2 DISABLED DISABLED PTA6/ LLWU_P2 TPM0_CH4 SPI0_MISO
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Pinout 48 LQFP 32 QFN 32 LQFP 24 QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 33 21 21 — PTA10/ IRQ_12 DISABLED TSI0_IN11 PTA10/ IRQ_12 34 22 22 — PTA11/ IRQ_13 DISABLED TSI0_IN10 PTA11/ IRQ_13 35 23 23 17 PTB3/ IRQ_14 DISABLED DISABLED PTB3/ IRQ_14 I2C0_SCL UART0_TX 36 24 24 18 PTB4/ IRQ_15/ LLWU_P6 DISABLED DISABLED PTB4/ IRQ_15/ LLWU_P6 I2C0_SDA UART0_RX 37 25 25 19 PTB5/ IRQ_16 NMI_b ADC0_SE1/ CMP0_IN1 PTB5/ IRQ_16 TPM1_CH1 NMI_b 38 26 26 20 PTA12/
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PTA2 PTA1/IRQ_1/LPTMR0_ALT1 PTA0/IRQ_0/LLWU_P7 PTB13 PTB17 PTB16 PTB15 PTA19 PTB12 PTA13 PTA12/IRQ_17/LPTMR0_ALT2 PTB5/IRQ_16 48 47 46 45 44 43 42 41 40 39 38 37 Pinout VREFL 7 30 VSS VSS 8 29 PTB20 PTA3 9 28 PTA9 PTA4/LLWU_P0 10 27 PTA8 VSS 11 26 PTB2/IRQ_10/LLWU_P5 PTB18 12 25 PTB1/IRQ_9 24 VDD PTB0/IRQ_8/LLWU_P4 31 23 6 PTA7/IRQ_7/LLWU_P3 VREFH 22 PTB14/IRQ_11 PTB11 32 21 5 PTB10 VDD 20 PTA10/IRQ_12 PTA18/IRQ_6 33 19 4 PTA17/IRQ_5 PT
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PTA2 PTA1/IRQ_1/LPTMR0_ALT1 PTA0/IRQ_0/LLWU_P7 PTB13 PTB12 PTA13 PTA12/IRQ_17/LPTMR0_ALT2 PTB5/IRQ_16 32 31 30 29 28 27 26 25 Pinout 21 PTA10/IRQ_12 VREFL 5 20 PTA9 VSS 6 19 PTA8 PTA3 7 18 PTB2/IRQ_10/LLWU_P5 PTA4/LLWU_P0 8 17 PTB1/IRQ_9 PTA6/LLWU_P2 PTA5/LLWU_P1/RTC_CLK_IN 16 4 PTB0/IRQ_8/LLWU_P4 VREFH 15 PTA11/IRQ_13 PTA7/IRQ_7/LLWU_P3 22 14 3 PTB11 VDD 13 PTB3/IRQ_14 PTB10 23 12 2 PTB9 PTB7/IRQ_3 11 PTB4/IRQ_15/LLWU_P6 PTB8 24 10 1 9 PTB6/IR
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PTA2 PTA1/IRQ_1/LPTMR0_ALT1 PTA0/IRQ_0/LLWU_P7 PTB13 PTB12 PTA13 PTA12/IRQ_17/LPTMR0_ALT2 PTB5/IRQ_16 32 31 30 29 28 27 26 25 Pinout 21 PTA10/IRQ_12 VREFL 5 20 PTA9 VSS 6 19 PTA8 PTA3 7 18 PTB2/IRQ_10/LLWU_P5 PTA4/LLWU_P0 8 17 PTB1/IRQ_9 PTA6/LLWU_P2 PTA5/LLWU_P1/RTC_CLK_IN 16 4 PTB0/IRQ_8/LLWU_P4 VREFH 15 PTA11/IRQ_13 PTA7/IRQ_7/LLWU_P3 22 14 3 PTB11 VDD 13 PTB3/IRQ_14 PTB10 23 12 2 PTB9 PTB7/IRQ_3 11 PTB4/IRQ_15/LLWU_P6 PTB8 24 10 1 9 PTB6/IR
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PTA2 PTA1/IRQ_1/LPTMR0_ALT1 PTA0/IRQ_0/LLWU_P7 PTB13 PTA12/IRQ_17/LPTMR0_ALT2 PTB5/IRQ_16 24 23 22 21 20 19 Ordering parts 3 16 PTA9 VREFL VSS 4 15 PTA8 PTA3 5 14 PTB2/IRQ_10/LLWU_P5 PTA4/LLWU_P0 6 13 PTB1/IRQ_9 PTB10 PTA6/LLWU_P2 PTA5/LLWU_P1/RTC_CLK_IN 12 VDD VREFH PTB0/IRQ_8/LLWU_P4 PTB3/IRQ_14 11 17 PTA7/IRQ_7/LLWU_P3 2 10 PTB7/IRQ_3 9 PTB4/IRQ_15/LLWU_P6 PTB11 18 8 1 7 PTB6/IRQ_2/LPTMR0_ALT3 Figure 20. KL05 24-pin QFN pinout diagram 6 Ordering parts 6.
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Part identification 7.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 7.2 Format Part numbers for this device have the following format: Q KL## A FFF R T PP CC N 7.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Table 35.
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Terminology and guidelines MKL05Z8VLC4 8 Terminology and guidelines 8.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 8.1.1 Example This is an example of an operating requirement: Symbol VDD Description 1.0 V core supply voltage Min. 0.9 Max. 1.1 Unit V 8.
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Terminology and guidelines Symbol CIN_D Description Input capacitance: digital pins Min. — Max. 7 Unit pF 8.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. 8.4.1 Example This is an example of an operating rating: Symbol VDD Description 1.0 V core supply voltage Min. –0.3 Max. 1.2 Unit V 8.
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Terminology and guidelines 8.6 Relationship between ratings and operating requirements O ra pe g tin g tin ( nt me ire ) n. mi ra g tin era Op ) in. (m u req ax g tin era Op (m nt me ire u req .) x.
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Terminology and guidelines 8.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol Description IWP Digital I/O weak pullup/pulldown current Min. 10 Typ. Max. 70 130 Unit µA 8.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 5000 4500 4000 TJ IDD_STOP (μA) 3500 150 °C 3000 105 °C 2500 25 °C 2000 –40 °C 1500 1000 500 0 0.90 0.95 1.00 1.05 1.10 VDD (V) 8.
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Revision history Table 36. Typical value conditions Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V 9 Revision history The following table provides a revision history for this document. Table 37. Revision history Rev. No. Date 2 9/2012 Initial public release. 3 11/2012 Completed all the TBDs. 4 3/2014 52 Freescale Semiconductor, Inc.
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How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein.