Datasheet

Table 10. Low power mode peripheral adders — typical value (continued)
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
I
TPM
TPM peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
configured for output compare
generating 100 Hz clock signal. No load
is placed on the I/O generating the
clock signal. Includes selected clock
source and I/O switching currents.
• MCGIRCLK (4 MHz internal
reference clock)
• OSCERCLK (4 MHz external
crystal)
86
235
86
256
86
265
86
274
86
280
86
287
µA
I
BG
Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
45 45 45 45 45 45 µA
I
ADC
ADC peripheral adder combining the
measured values at V
DD
and V
DDA
by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
366 366 366 366 366 366 µA
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE for run mode, and BLPE for VLPR mode
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
General
Kinetis KL05 32 KB Flash, Rev4 03/2014. 13
Freescale Semiconductor, Inc.