Datasheet

Table 16. SWD full voltage range electricals (continued)

Symbol Description Min. Max. Unit

• Serial wire debug 20 — ns

J4 SWD_CLK rise and fall times — 3 ns

J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns

J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns

J11 SWD_CLK high to SWD_DIO data valid — 32 ns

J12 SWD_CLK high to SWD_DIO high-Z 5 — ns

J3 J3

J4 J4

SWD_CLK (input)

Figure 4. Serial wire clock input timing

J11

J12

J11

J10

Input data valid

Output data valid

SWD_CLK

SWD_DIO

Figure 5. Serial wire data timing

Peripheral operating requirements and behaviors

Kinetis KL05 32 KB Flash, Rev4 03/2014. 19

Freescale Semiconductor, Inc.