Datasheet

Table 24. 12-bit ADC operating conditions (continued)
Symbol Description Conditions Min. Typ.
1
Max. Unit Notes
R
AS
Analog source
resistance
(external)
12-bit modes
f
ADCK
< 4 MHz — — 5 kΩ
4
f
ADCK
ADC conversion
clock frequency
≤ 12-bit mode 1.0 — 18.0 MHz 5
C
rate
ADC conversion
rate
≤ 12-bit modes
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
20.000 — 818.330 Ksps
6
1. Typical values assume V
DDA
= 3.0 V, Temp = 25 °C, f
ADCK
= 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. For packages without dedicated VREFH and VREFL pins, V
REFH
is internally tied to V
DDA
, and V
REFL
is internally tied to
V
SSA
.
4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The R
AS
/
C
AS
time constant should be kept to < 1 ns.
5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
RAS
VAS
CAS
ZAS
VADIN
ZADIN
RADIN
RADIN
RADIN
RADIN
CADIN
Pad
leakage
due to
input
protection
INPUT PIN
INPUT PIN
INPUT PIN
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
ADC SAR
ENGINE
Figure 6. ADC input impedance equivalency diagram
Peripheral operating requirements and behaviors
26 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.