Datasheet

3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (V
REFH
- V
REFL
)/2
N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. ADC conversion clock < 3 MHz
Figure 7. Typical ENOB vs. ADC_CLK for 12-bit single-ended mode
3.6.2 CMP and 6-bit DAC electrical specifications
Table 26. Comparator and 6-bit DAC electrical specifications
Symbol Description Min. Typ. Max. Unit
V
DD
Supply voltage 1.71 — 3.6 V
I
DDHS
Supply current, high-speed mode (EN = 1, PMODE =
1)
— — 200 μA
I
DDLS
Supply current, low-speed mode (EN = 1, PMODE =
0)
— — 20 μA
V
AIN
Analog input voltage V
SS
— V
DD
V
V
AIO
Analog input offset voltage — — 20 mV
V
H
Analog comparator hysteresis
1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
—
—
5
10
—
—
mV
mV
Table continues on the next page...
Peripheral operating requirements and behaviors
28 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.