Datasheet

3.8.1 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following
tables provide timing characteristics for classic SPI timing modes. See the SPI chapter
of the chip's Reference Manual for information about the modified transfer formats used
for communicating with slower peripheral devices.
All timing is shown with respect to 20% V
DD
and 80% V
DD
thresholds, unless noted, as
well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 29. SPI master mode timing on slew rate disabled pads
Num. Symbol Description Min. Max. Unit Note
1 f
op
Frequency of operation f
periph
/2048 f
periph
/2 Hz 1
2 t
SPSCK
SPSCK period 2 x t
periph
2048 x
t
periph
ns 2
3 t
Lead
Enable lead time 1/2 — t
SPSCK
—
4 t
Lag
Enable lag time 1/2 — t
SPSCK
—
5 t
WSPSCK
Clock (SPSCK) high or low time t
periph
– 30 1024 x
t
periph
ns —
6 t
SU
Data setup time (inputs) 16 — ns —
7 t
HI
Data hold time (inputs) 0 — ns —
8 t
v
Data valid (after SPSCK edge) — 10 ns —
9 t
HO
Data hold time (outputs) 0 — ns —
10 t
RI
Rise time input — t
periph
– 25 ns —
t
FI
Fall time input
11 t
RO
Rise time output — 25 ns —
t
FO
Fall time output
1. For SPI0, f
periph
is the bus clock (f
BUS
).
2. t
periph
= 1/f
periph
Table 30. SPI master mode timing on slew rate enabled pads
Num. Symbol Description Min. Max. Unit Note
1 f
op
Frequency of operation f
periph
/2048 f
periph
/2 Hz 1
2 t
SPSCK
SPSCK period 2 x t
periph
2048 x
t
periph
ns 2
3 t
Lead
Enable lead time 1/2 — t
SPSCK
—
4 t
Lag
Enable lag time 1/2 — t
SPSCK
—
5 t
WSPSCK
Clock (SPSCK) high or low time t
periph
– 30 1024 x
t
periph
ns —
6 t
SU
Data setup time (inputs) 96 — ns —
7 t
HI
Data hold time (inputs) 0 — ns —
Table continues on the next page...
Peripheral operating requirements and behaviors
34 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.