Datasheet

<<CLASSIFICATION>>
<<NDA MESSAGE>>
38
2
6 7
MSB IN
2
BIT 6 . . . 1
MASTER MSB OUT
2
MASTER LSB OUT
5
5
8
10 11
PORT DATA
PORT DATA
3
10 11 4
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
9
(OUTPUT)
(CPOL=0)
SPSCK
SPSCK
(CPOL=1)
SS
1
(OUTPUT)
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT)
LSB IN
BIT 6 . . . 1
Figure 13. SPI master mode timing (CPHA = 1)
Table 31. SPI slave mode timing on slew rate disabled pads
Num. Symbol Description Min. Max. Unit Note
1 f
op
Frequency of operation 0 f
periph
/4 Hz 1
2 t
SPSCK
SPSCK period 4 x t
periph
— ns 2
3 t
Lead
Enable lead time 1 — t
periph
—
4 t
Lag
Enable lag time 1 — t
periph
—
5 t
WSPSCK
Clock (SPSCK) high or low time t
periph
– 30 — ns —
6 t
SU
Data setup time (inputs) 2 — ns —
7 t
HI
Data hold time (inputs) 7 — ns —
8 t
a
Slave access time — t
periph
ns 3
9 t
dis
Slave MISO disable time — t
periph
ns 4
10 t
v
Data valid (after SPSCK edge) — 22 ns —
11 t
HO
Data hold time (outputs) 0 — ns —
12 t
RI
Rise time input — t
periph
– 25 ns —
t
FI
Fall time input
13 t
RO
Rise time output — 25 ns —
t
FO
Fall time output
1. For SPI0, f
periph
is the bus clock (f
BUS
).
2. t
periph
= 1/f
periph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
Peripheral operating requirements and behaviors
36 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.