Datasheet

48
LQFP
32
QFN
32
LQFP
24
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3
33 21 21 — PTA10/
IRQ_12
DISABLED TSI0_IN11 PTA10/
IRQ_12
34 22 22 — PTA11/
IRQ_13
DISABLED TSI0_IN10 PTA11/
IRQ_13
35 23 23 17 PTB3/
IRQ_14
DISABLED DISABLED PTB3/
IRQ_14
I2C0_SCL UART0_TX
36 24 24 18 PTB4/
IRQ_15/
LLWU_P6
DISABLED DISABLED PTB4/
IRQ_15/
LLWU_P6
I2C0_SDA UART0_RX
37 25 25 19 PTB5/
IRQ_16
NMI_b ADC0_SE1/
CMP0_IN1
PTB5/
IRQ_16
TPM1_CH1 NMI_b
38 26 26 20 PTA12/
IRQ_17/
LPTMR0_ALT2
ADC0_SE0/
CMP0_IN0
ADC0_SE0/
CMP0_IN0
PTA12/
IRQ_17/
LPTMR0_ALT2
TPM1_CH0 TPM_CLKIN0
39 27 27 — PTA13 TSI0_IN9 TSI0_IN9 PTA13
40 28 28 — PTB12 TSI0_IN8 TSI0_IN8 PTB12
41 — — — PTA19 DISABLED DISABLED PTA19 SPI0_SS_b
42 — — — PTB15 DISABLED DISABLED PTB15 SPI0_MOSI SPI0_MISO
43 — — — PTB16 DISABLED DISABLED PTB16 SPI0_MISO SPI0_MOSI
44 — — — PTB17 DISABLED DISABLED PTB17 TPM_CLKIN1 SPI0_SCK
45 29 29 21 PTB13 ADC0_SE13 ADC0_SE13 PTB13 TPM1_CH1 RTC_CLKOUT
46 30 30 22 PTA0/
IRQ_0/
LLWU_P7
SWD_CLK ADC0_SE12/
CMP0_IN2
PTA0/
IRQ_0/
LLWU_P7
TPM1_CH0 SWD_CLK
47 31 31 23 PTA1/
IRQ_1/
LPTMR0_ALT1
RESET_b DISABLED PTA1/
IRQ_1/
LPTMR0_ALT1
TPM_CLKIN0 RESET_b
48 32 32 24 PTA2 SWD_DIO DISABLED PTA2 CMP0_OUT SWD_DIO
5.2 KL05 pinouts
The following figures show the pinout diagrams for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see KL05 signal multiplexing and pin assignments.
Pinout
42 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.