Datasheet

Table 7. Voltage and current operating behaviors (continued)
Symbol Description Min. Max. Unit Notes
V
OL
Output low voltage — High drive pad
• 2.7 V ≤ V
DD
≤ 3.6 V, I
OL
= 18 mA
• 1.71 V ≤ V
DD
≤ 2.7 V, I
OL
= 6 mA
—
—
0.5
0.5
V
V
1
I
OLT
Output low current total for all ports — 100 mA
I
IN
Input leakage current (per pin) for full temperature
range
— 1 μA 3
I
IN
Input leakage current (per pin) at 25 °C — 0.025 μA 3
I
IN
Input leakage current (total all pins) for full
temperature range
— 41 μA 3
I
OZ
Hi-Z (off-state) leakage current (per pin) — 1 μA
R
PU
Internal pullup resistors 20 50 kΩ 4
1. PTA12, PTA13, PTB0 and PTB1 I/O have both high drive and normal drive capability selected by the associated
PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When
configured as a GPIO output, it acts as a pseudo open drain output.
3. Measured at V
DD
= 3.6 V
4. Measured at V
DD
supply voltage = V
DD
min and Vinput = V
SS
2.2.4 Power mode transition operating behaviors
All specifications except t
POR
and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• FEI clock mode
POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system
frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.
Table 8. Power mode transition operating behaviors
Symbol Description Min. Typ. Max. Unit
t
POR
After a POR event, amount of time from the
point V
DD
reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
— — 300 μs 1
• VLLS0 → RUN
— 95 115 μs
• VLLS1 → RUN
Table continues on the next page...
General
8 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.