Datasheet

80.00E-03
100.00E-03
120.00E-03
140.00E-03
160.00E-03
180.00E-03
CMP Hysteresis (V)
CMP Hysteresis vs Vinn
0
1
2
HYSTCTR
Setting
-20.00E-03
000.00E+00
20.00E-03
40.00E-03
60.00E-03
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
CMP Hysteresis (V)
Vinn (V)
3
Figure 9. Typical hysteresis vs. Vin level (V
DD
= 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
3.6.3.1 12-bit DAC operating requirements
Table 27. 12-bit DAC operating requirements
Symbol Desciption Min. Max. Unit Notes
V
DDA
Supply voltage 3.6 V
V
DACR
Reference voltage 1.13 3.6 V 1
C
L
Output load capacitance — 100 pF 2
I
L
Output load current — 1 mA
1. The DAC reference can be selected to be V
DDA
or V
REFH
.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
3.6.3.2 12-bit DAC operating behaviors
Table 28. 12-bit DAC operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
I
DDA_DACL
P
Supply current — low-power mode — — 250 μA
I
DDA_DACH
P
Supply current — high-speed mode — — 900 μA
t
DACLP
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
— 100 200 μs 1
t
DACHP
Full-scale settling time (0x080 to 0xF7F) —
high-power mode
— 15 30 μs 1
Table continues on the next page...
Peripheral operating requirements and behaviors
30 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.