Datasheet

Table 30. SPI master mode timing on slew rate enabled pads (continued)
Num. Symbol Description Min. Max. Unit Note
8 t
v
Data valid (after SPSCK edge) — 52 ns —
9 t
HO
Data hold time (outputs) 0 — ns —
10 t
RI
Rise time input — t
periph
– 25 ns —
t
FI
Fall time input
11 t
RO
Rise time output — 36 ns —
t
FO
Fall time output
1. For SPI0, f
periph
is the bus clock (f
BUS
).
2. t
periph
= 1/f
periph
(OUTPUT)
2
8
6 7
MSB IN
2
LSB IN
MSB OUT
2
LSB OUT
9
5
5
3
(CPOL=0)
4
11
11
10
10
SPSCK
SPSCK
(CPOL=1)
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1. If configured as an output.
SS
1
(OUTPUT)
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT)
BIT 6 . . . 1
BIT 6 . . . 1
Figure 12. SPI master mode timing (CPHA = 0)
Peripheral operating requirements and behaviors
Kinetis KL05 32 KB Flash, Rev4 03/2014. 35
Freescale Semiconductor, Inc.