Datasheet

Table 32. SPI slave mode timing on slew rate enabled pads
Num. Symbol Description Min. Max. Unit Note
1 f
op
Frequency of operation 0 f
periph
/4 Hz 1
2 t
SPSCK
SPSCK period 4 x t
periph
— ns 2
3 t
Lead
Enable lead time 1 — t
periph
—
4 t
Lag
Enable lag time 1 — t
periph
—
5 t
WSPSCK
Clock (SPSCK) high or low time t
periph
– 30 — ns —
6 t
SU
Data setup time (inputs) 2 — ns —
7 t
HI
Data hold time (inputs) 7 — ns —
8 t
a
Slave access time — t
periph
ns 3
9 t
dis
Slave MISO disable time — t
periph
ns 4
10 t
v
Data valid (after SPSCK edge) — 122 ns —
11 t
HO
Data hold time (outputs) 0 — ns —
12 t
RI
Rise time input — t
periph
– 25 ns —
t
FI
Fall time input
13 t
RO
Rise time output — 36 ns —
t
FO
Fall time output
1. For SPI0, f
periph
is the bus clock (f
BUS
).
2. t
periph
= 1/f
periph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
2
10
6 7
MSB IN
BIT 6 . . . 1
SLAVE MSB
SLAVE LSB OUT
11
5
5
3
8
4
13
NOTE: Not defined
12
12
11
SEE
NOTE
13
9
see
note
(INPUT)
(CPOL=0)
SPSCK
SPSCK
(CPOL=1)
SS
(INPUT)
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
LSB IN
BIT 6 . . . 1
Figure 14. SPI slave mode timing (CPHA = 0)
Peripheral operating requirements and behaviors
Kinetis KL05 32 KB Flash, Rev4 03/2014. 37
Freescale Semiconductor, Inc.