Datasheet

2
6 7
MSB IN
BIT 6 . . . 1
MSB OUT SLAVE LSB OUT
5
5
10
12 13
3
12 13
4
SLAVE
8
9
see
note
(INPUT)
(CPOL=0)
SPSCK
SPSCK
(CPOL=1)
SS
(INPUT)
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
NOTE: Not defined
11
LSB IN
BIT 6 . . . 1
Figure 15. SPI slave mode timing (CPHA = 1)
3.8.2 Inter-Integrated Circuit Interface (I2C) timing
Table 33. I2C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency f
SCL
0 100 0 400
1
kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
t
HD
; STA 4 — 0.6 — µs
LOW period of the SCL clock t
LOW
4.7 — 1.3 — µs
HIGH period of the SCL clock t
HIGH
4 — 0.6 — µs
Set-up time for a repeated START
condition
t
SU
; STA 4.7 — 0.6 — µs
Data hold time for I
2
C bus devices t
HD
; DAT 0
2
3.45
3
0
4
0.9
2
µs
Data set-up time t
SU
; DAT 250
5
— 100
3
,
6
— ns
Rise time of SDA and SCL signals t
r
— 1000 20 +0.1C
b
7
300 ns
Fall time of SDA and SCL signals t
f
— 300 20 +0.1C
b
6
300 ns
Set-up time for STOP condition t
SU
; STO 4 — 0.6 — µs
Bus free time between STOP and
START condition
t
BUF
4.7 — 1.3 — µs
Pulse width of spikes that must be
suppressed by the input filter
t
SP
N/A N/A 0 50 ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only achieved when using the High
drive pins (see Voltage and current operating behaviors) or when using the Normal drive pins and VDD ≥ 2.7 V
Peripheral operating requirements and behaviors
38 Kinetis KL05 32 KB Flash, Rev4 03/2014.
Freescale Semiconductor, Inc.