Datasheet

2. The master mode I
2
C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and
SCL lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I
2
C bus device can be used in a Standard mode I2C bus system, but the requirement t
SU; DAT
≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t
rmax
+ t
SU; DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I
2
C bus specification) before the SCL line is
released.
7. C
b
= total capacitance of the one bus line in pF.


SDA
SCL
t
HD; STA
t
HD; DAT
t
LOW
t
SU; DAT
t
HIGH
t
SU; STA
SR
P
S
S
t
HD; STA
t
SP
t
SU; STO
t
BUF
t
f
t
r
t
f
t
r
Figure 16. Timing definition for fast and standard mode devices on the I
2
C bus
3.8.3 UART
See General switching specifications.
3.9 Human-machine interfaces (HMI)
3.9.1 TSI electrical specifications
Table 34. TSI electrical specifications
Symbol Description Min. Typ. Max. Unit
TSI_RUNF Fixed power consumption in run mode — 100 — µA
TSI_RUNV Variable power consumption in run mode
(depends on oscillator's current selection)
1.0 — 128 µA
TSI_EN Power consumption in enable mode — 100 — µA
TSI_DIS Power consumption in disable mode — 1.2 — µA
TSI_TEN TSI analog enable time — 66 — µs
TSI_CREF TSI reference capacitor — 1.0 — pF
TSI_DVOLT Voltage variation of VP & VM around nominal
values
0.19 — 1.03 V
Peripheral operating requirements and behaviors
Kinetis KL05 32 KB Flash, Rev4 03/2014. 39
Freescale Semiconductor, Inc.