Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFN 32 (5x5) 32-Bit 48 MHz I/O number 23

Kinetis KL24 Sub-Family

48 MHz Cortex-M0+ Based Microcontroller with USB

Designed with efficiency in mind. Compatible with all other

Kinetis L families as well as Kinetis K2x family. General purpose

MCU with USB 2.0, featuring market leading ultra low-power to

provide developers an appropriate entry-level 32-bit solution.

This product offers:

• Run power consumption down to 47 μA/MHz in very low

power run mode

• Static power consumption down to 2 μA with full state

retention and 4 μs wakeup

• Ultra-efficient Cortex-M0+ processor running up to 48 MHz

with industry leading throughput

• Memory option is up to 128 KB flash and 16 KB RAM

• Energy-saving architecture is optimized for low power with

90 nm TFS technology, clock and power gating techniques,

and zero wait state flash memory controller

Performance

• 48 MHz ARM

Cortex

-M0+ core

Memories and memory interfaces

• Up to 64 KB program flash memory

• Up to 8 KB SRAM

System peripherals

• Nine low-power modes to provide power optimization

based on application requirements

• COP Software watchdog

• 4-channel DMA controller, supporting up to 63 request

sources

• Low-leakage wakeup unit

• SWD debug interface and Micro Trace Buffer

• Bit Manipulation Engine

Clocks

• 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator

• Multi-purpose clock source

• 1 kHz LPO clock

Operating Characteristics

• Voltage range: 1.71 to 3.6 V

Human-machine interface

• Up to 66 general-purpose input/output (GPIO)

Communication interfaces

• USB full-/low-speed On-the-Go controller with on-

chip transceiver and 5 V to 3.3 V regulator

• Two 8-bit SPI modules

• One low power UART module

• Two UART modules

• Two I2C module

Analog Modules

• 12-bit SAR ADC

• Analog comparator (CMP) containing a 6-bit DAC

and programmable reference input

Timers

• Six channel Timer/PWM (TPM)

• Two 2-channel Timer/PWM modules

• Periodic interrupt timers

• 16-bit low-power timer (LPTMR)

• Real time clock

Security and integrity modules

• 80-bit unique identification number per chip

MKL24ZxxVFM4

MKL24ZxxVFT4

MKL24ZxxVLH4

MKL24ZxxVLK4

32-pin QFN (FM)

5 x 5 x 1 Pitch 0.5 mm

48-pin QFN (FT)

7 x 7 x 1 Pitch 0.5 mm

64-pin LQFP (LH)

10 x 10 x 1.4 Pitch 0.5

80-pin LQFP (LK)

12 x 12 x 1.4 Pitch 0.5

Freescale Semiconductor, Inc.

KL24P80M48SF0

Data Sheet: Technical Data Rev 4 03/2014

Freescale reserves the right to change the detail specifications as may be required to

Summary of content (53 pages)

PAGE 1
Freescale Semiconductor, Inc. Data Sheet: Technical Data KL24P80M48SF0 Rev 4 03/2014 Kinetis KL24 Sub-Family MKL24ZxxVFM4 MKL24ZxxVFT4 MKL24ZxxVLH4 MKL24ZxxVLK4 48 MHz Cortex-M0+ Based Microcontroller with USB Designed with efficiency in mind. Compatible with all other Kinetis L families as well as Kinetis K2x family. General purpose MCU with USB 2.0, featuring market leading ultra low-power to provide developers an appropriate entry-level 32-bit solution.
PAGE 2
• Flash write voltage range: 1.71 to 3.
PAGE 3
Table of Contents 1 Ratings..................................................................................4 1.1 Thermal handling ratings...............................................4 1.2 Moisture handling ratings...............................................4 1.3 ESD handling ratings.....................................................4 1.4 Voltage and current operating ratings............................4 2 General.................................................................................5 2.
PAGE 4
Ratings 1 Ratings 1.1 Thermal handling ratings Table 1. Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.2 Moisture handling ratings Table 2.
PAGE 5
General 1.4 Voltage and current operating ratings Table 4. Voltage and current operating ratings Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V IDD Digital supply current — 120 mA VIO IO pin input voltage –0.3 VDD + 0.3 V Instantaneous maximum current single pin limit (applies to all port pins) –25 25 mA ID VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V VUSB_DP USB_DP input voltage –0.3 3.63 V VUSB_DM USB_DM input voltage –0.3 3.
PAGE 6
General 2.2 Nonswitching electrical specifications 2.2.1 Voltage and current operating requirements Table 5. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V — VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V — VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V — VIH VIL Input high voltage — • 2.7 V ≤ VDD ≤ 3.6 V 0.7 × VDD — V • 1.7 V ≤ VDD ≤ 2.7 V 0.
PAGE 7
General Table 6. VDD supply LVD and POR operating requirements (continued) Symbol Description Min. Typ. Max. Unit Notes Low-voltage warning thresholds — high range 1 VLVW1H • Level 1 falling (LVWV = 00) 2.62 2.70 2.78 V VLVW2H • Level 2 falling (LVWV = 01) 2.72 2.80 2.88 V VLVW3H • Level 3 falling (LVWV = 10) 2.82 2.90 2.98 V VLVW4H • Level 4 falling (LVWV = 11) 2.92 3.00 3.08 V — ±60 — mV — 1.54 1.60 1.
PAGE 8
General Table 7. Voltage and current operating behaviors (continued) Symbol Description • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA Min. Max. Unit — 0.5 V Notes • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA VOL Output low voltage — High drive pad 1 • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA — 0.
PAGE 9
General Table 8. Power mode transition operating behaviors (continued) Symbol Description Min. Typ. Max. Unit — 95 115 μs — 93 115 μs — 42 53 μs — 4 4.6 μs — 4 4.4 μs — 4 4.4 μs instruction across the operating temperature range of the chip. • VLLS0 → RUN • VLLS1 → RUN • VLLS3 → RUN • LLS → RUN • VLPS → RUN • STOP → RUN 1. Normal boot (FTFA_FOPT[LPBOOT]=11). 2.2.5 Power consumption operating behaviors Table 9.
PAGE 10
General Table 9. Power consumption operating behaviors (continued) Symbol Description • at 3.0 V Min. Typ. Max. Unit — 6.8 8.3 mA — 3.7 5.0 mA — 2.9 4.2 mA — 2.5 3.7 mA — 188 570 μA — 224 613 μA — 300 745 μA — 135 496 μA — 345 490 μA — 357 827 — 392 869 — 438 927 — 551 1065 — 4.
PAGE 11
General Table 9. Power consumption operating behaviors (continued) Symbol Min. Typ. Max. Unit at 25 °C Description — 10 35 μA at 50 °C — 20 50 at 70 °C — 37 112 at 85 °C — 81 201 1.9 3.7 3.6 39 6.5 43 13 49 30 69 — 1.4 3.2 — 2.5 19 — 5.1 21 — 9.2 26 — 21 38 — 0.7 — 1.3 — 2.3 — 5.1 — 13 — 381 — 956 — 2370 — 4800 — 12410 — 176 — 760 — 2120 — 4500 — 12130 Notes at 105 °C IDD_LLS Low-leakage stop mode current at 3.
PAGE 12
General 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. MCG configured for PEE mode. CoreMark benchmark compiled using Keil 4.54 with optimization level 3, optimized for time. 3. MCG configured for FEI mode. 4. Incremental current consumption from peripheral activity is not included. 5. MCG configured for BLPI mode. 6. No brownout Table 10.
PAGE 13
General Table 10. Low power mode peripheral adders — typical value (continued) Symbol Description Temperature (°C) Unit -40 25 50 70 85 105 86 86 86 86 86 86 235 256 265 274 280 287 • MCGIRCLK (4 MHz internal reference clock) • OSCERCLK (4 MHz external crystal) ITPM TPM peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source configured for output compare generating 100 Hz clock signal. No load is placed on the I/O generating the clock signal.
PAGE 14
General Run Mode Current Vs Core Frequency Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE 8.00E-03 7.00E-03 Current Consumption on VDD(A) 6.00E-03 5.00E-03 All Peripheral CLK Gates 4.00E-03 All Off All On 3.00E-03 2.00E-03 1.00E-03 000.00E+00 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-2 1 2 3 4 6 12 24 48 CLK Ratio Flash-Core Core Freq (MHz) Figure 2. Run mode supply current vs. core frequency 14 Freescale Semiconductor, Inc.
PAGE 15
General VLPR Mode Current Vs Core Frequency Temperature = 25, V DD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE 400.00E-06 Current Consumption on VDD (A) 350.00E-06 300.00E-06 250.00E-06 All Peripheral CLK Gates 200.00E-06 All Off All On 150.00E-06 100.00E-06 50.00E-06 000.00E+00 '1-1 '1-2 1 '1-2 '1-4 2 4 CLK Ratio Flash-Core Core Freq (MHz) Figure 3. VLPR mode current vs. core frequency 2.2.6 EMC radiated emissions operating behaviors Table 11.
PAGE 16
General application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. VDD = 3.3 V, TA = 25 °C, fOSC = 8 MHz (crystal), fSYS = 48 MHz, fBUS = 48 MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method 2.2.
PAGE 17
General Table 13. Device clock specifications (continued) Symbol fERCLK Description Min. Max. Unit — 16 MHz — 16 MHz Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x) — 16 MHz TPM asynchronous clock — 8 MHz UART0 asynchronous clock — 8 MHz External reference clock fLPTMR_ERCLK LPTMR external reference clock fosc_hi_2 fTPM fUART0 1.
PAGE 18
Peripheral operating requirements and behaviors 2.4.2 Thermal attributes Table 16. Thermal attributes Board type Symbol Single-layer (1S) RθJA Four-layer (2s2p) Description 80 LQFP 64 LQFP 48 QFN 32 QFN Unit Notes Thermal resistance, junction to ambient (natural convection) 70 71 84 92 °C/W 1 RθJA Thermal resistance, junction to ambient (natural convection) 53 52 28 33 °C/W Single-layer (1S) RθJMA Thermal resistance, junction to ambient (200 ft./min.
PAGE 19
Peripheral operating requirements and behaviors 3.1.1 SWD electricals Table 17. SWD full voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 1.71 3.
PAGE 20
Peripheral operating requirements and behaviors SWD_CLK J9 SWD_DIO J10 Input data valid J11 SWD_DIO Output data valid J12 SWD_DIO J11 SWD_DIO Output data valid Figure 5. Serial wire data timing 3.2 System modules There are no specifications necessary for the device's system modules. 3.3 Clock modules 3.3.1 MCG specifications Table 18. MCG specifications Symbol Description Min. Typ. Max.
PAGE 21
Peripheral operating requirements and behaviors Table 18. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit Notes Δfdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature — +0.5/-0.7 ±3 %fdco 1, 2 Δfdco_t Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0–70 °C — ± 0.4 ± 1.
PAGE 22
Peripheral operating requirements and behaviors Table 18. MCG specifications (continued) Symbol Description Min. Jacc_pll PLL accumulated jitter over 1µs (RMS) Typ. Max. Unit 10 • fvco = 48 MHz — 1350 — ps • fvco = 100 MHz — 600 — ps Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time Notes — — 10-6 150 × + 1075(1/ fpll_ref) s 11 1.
PAGE 23
Peripheral operating requirements and behaviors Table 19. Oscillator DC electrical specifications (continued) Symbol Description • 24 MHz Min. Typ. Max. Unit — 1.5 — mA Notes • 32 MHz IDDOSC Supply current — high gain mode (HGO=1) 1 • 32 kHz — 25 — μA • 4 MHz — 400 — μA • 8 MHz (RANGE=01) — 500 — μA • 16 MHz — 2.
PAGE 24
Peripheral operating requirements and behaviors 3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all other cases external capacitors must be used. 4. When low power mode is selected, RF is integrated and must not be attached externally. 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.2.2 Symbol Oscillator frequency specifications Table 20.
PAGE 25
Peripheral operating requirements and behaviors 3.4.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 21. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit thvpgm4 Notes Longword Program high-voltage time — 7.
PAGE 26
Peripheral operating requirements and behaviors 3.4.1.4 Symbol Reliability specifications Table 24. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash tnvmretp10k Data retention after up to 10 K cycles 5 50 — years tnvmretp1k Data retention after up to 1 K cycles 20 100 — years nnvmcycp Cycling endurance 10 K 50 K — cycles 2 1.
PAGE 27
Peripheral operating requirements and behaviors Table 25. 12-bit ADC operating conditions (continued) Min. Typ.1 Symbol Description Conditions Max. Unit RAS Analog source resistance (external) 12-bit modes fADCK < 4 MHz — — 5 kΩ fADCK ADC conversion clock frequency ≤ 12-bit mode 1.0 — 18.0 MHz Crate ADC conversion rate ≤ 12-bit modes Notes 4 5 6 No ADC hardware averaging 20.000 — 818.330 Ksps Continuous conversions enabled, subsequent conversion time 1.
PAGE 28
Peripheral operating requirements and behaviors 3.6.1.2 12-bit ADC electrical characteristics Table 26. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description IDDA_ADC Supply current ADC asynchronous clock source fADACK Conditions1 • ADLPC = 1, ADHSC = 0 • ADLPC = 1, ADHSC = 1 • ADLPC = 0, ADHSC = 0 Min. Typ.2 Max. Unit Notes 0.215 — 1.7 mA 3 1.2 2.4 3.9 MHz 2.4 4.0 6.1 MHz tADACK = 1/ fADACK 3.0 5.2 7.3 MHz 4.4 6.2 9.
PAGE 29
Peripheral operating requirements and behaviors 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. ADC conversion clock < 3 MHz Figure 7. Typical ENOB vs. ADC_CLK for 12-bit single-ended mode 3.
PAGE 30
Peripheral operating requirements and behaviors Table 27. Comparator and 6-bit DAC electrical specifications (continued) Symbol Description • CR0[HYSTCTR] = 10 Min. Typ. Max. Unit — 30 — mV • CR0[HYSTCTR] = 11 VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.
PAGE 31
Peripheral operating requirements and behaviors CMP Hysteresis vs Vinn 180.00E-03 160.00E-03 140.00E-03 CMP Hysteresis (V) 120.00E-03 HYSTCTR Setting 100.00E-03 0 1 80.00E-03 2 3 60.00E-03 40.00E-03 20.00E-03 000.00E+00 0.1 0.4 0.7 1 1.3 -20.00E-03 1.6 1.9 2.2 2.5 2.8 3.1 Vinn (V) Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 3.7 Timers See General switching specifications. 3.8 Communication interfaces 3.8.
PAGE 32
Peripheral operating requirements and behaviors Table 28. USB VREG electrical specifications (continued) Symbol Description • VREGIN = 5.0 V and temperature=25 °C Min. Typ.1 Max. Unit — — 4 μA Notes • Across operating voltage and temperature ILOADrun Maximum load current — Run mode — — 120 mA ILOADstby Maximum load current — Standby mode — — 1 mA 3 3.3 3.6 V 2.1 2.8 3.6 V 2.1 — 3.6 V VReg33out Regulator output voltage — Input supply (VREGIN) > 3.
PAGE 33
Peripheral operating requirements and behaviors Table 29. SPI master mode timing on slew rate disabled pads (continued) Num. Symbol Description 5 tWSPSCK Clock (SPSCK) high or low time 6 tSU 7 tHI 8 tv 9 10 11 Min. Max.
PAGE 34
Peripheral operating requirements and behaviors SS 1 (OUTPUT) 3 2 SPSCK (CPOL=0) (OUTPUT) 10 11 10 11 4 5 5 SPSCK (CPOL=1) (OUTPUT) 6 MISO (INPUT) 7 MSB IN 2 BIT 6 . . . 1 LSB IN 8 MOSI (OUTPUT) MSB OUT 2 9 BIT 6 . . . 1 LSB OUT 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 10.
PAGE 35
Peripheral operating requirements and behaviors Table 31. SPI slave mode timing on slew rate disabled pads (continued) Num. Symbol 4 tLag 5 tWSPSCK 6 tSU Data setup time (inputs) 7 tHI Data hold time (inputs) 8 ta Slave access time 9 tdis Slave MISO disable time 10 tv 11 12 13 1. 2. 3. 4. Description Min. Max.
PAGE 36
Peripheral operating requirements and behaviors SS (INPUT) 2 12 13 12 13 4 SPSCK (CPOL=0) (INPUT) 5 3 SPSCK (CPOL=1) (INPUT) 5 9 8 see note MISO (OUTPUT) SLAVE MSB 6 MOSI (INPUT) 10 11 11 BIT 6 . . . 1 SLAVE LSB OUT SEE NOTE 7 MSB IN BIT 6 . . . 1 LSB IN NOTE: Not defined Figure 12. SPI slave mode timing (CPHA = 0) SS (INPUT) 4 2 3 SPSCK (CPOL=0) (INPUT) 5 SPSCK (CPOL=1) (INPUT) 5 see note SLAVE 8 MSB OUT 6 MOSI (INPUT) 13 12 13 11 10 MISO (OUTPUT) 12 9 BIT 6 . .
PAGE 37
Peripheral operating requirements and behaviors 3.8.4 Inter-Integrated Circuit Interface (I2C) timing Table 33. I2C timing Characteristic Symbol Standard Mode Fast Mode Unit Minimum Maximum Minimum Maximum SCL Clock Frequency fSCL 0 100 0 4001 kHz Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 4 — 0.6 — µs LOW period of the SCL clock tLOW 4.7 — 1.3 — µs HIGH period of the SCL clock tHIGH 4 — 0.
PAGE 38
Dimensions 3.8.5 UART See General switching specifications. 4 Dimensions 4.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 32-pin QFN 98ASA00473D 48-pin QFN 98ASA00466D 64-pin LQFP 98ASS23234W 80-pin LQFP 98ASS23174W 5 Pinout 5.
PAGE 39
Pinout 80 64 LQFP LQFP 48 QFN 32 QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 6 — — — PTE5 DISABLED 7 3 1 — VDD VDD VDD 8 4 2 2 VSS VSS VSS 9 5 3 3 USB0_DP USB0_DP USB0_DP 10 6 4 4 USB0_DM USB0_DM USB0_DM 11 7 5 5 VOUT33 VOUT33 VOUT33 12 8 6 6 VREGIN VREGIN VREGIN 13 9 7 — PTE20 ADC0_SE0 ADC0_SE0 PTE20 TPM1_CH0 UART0_TX 14 10 8 — PTE21 ADC0_SE4a ADC0_SE4a PTE21 TPM1_CH1 UART0_RX 15 11 — — PTE22 ADC0_SE3 AD
PAGE 40
Pinout 80 64 LQFP LQFP 48 QFN 32 QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 43 35 27 20 PTB0/ LLWU_P5 ADC0_SE8 ADC0_SE8 PTB0/ LLWU_P5 I2C0_SCL TPM1_CH0 44 36 28 21 PTB1 ADC0_SE9 ADC0_SE9 PTB1 I2C0_SDA TPM1_CH1 45 37 29 — PTB2 ADC0_SE12 ADC0_SE12 PTB2 I2C0_SCL TPM2_CH0 46 38 30 — PTB3 ADC0_SE13 ADC0_SE13 PTB3 I2C0_SDA TPM2_CH1 47 — — — PTB8 DISABLED PTB8 48 — — — PTB9 DISABLED PTB9 49 — — — PTB10 DISABLED PTB10 SPI1_PCS0 ALT4 ALT5 — — —
PAGE 41
Pinout 80 64 LQFP LQFP 48 QFN 32 QFN Pin Name Default 77 61 45 29 PTD4/ LLWU_P14 DISABLED 78 62 46 30 PTD5 ADC0_SE6b 79 63 47 31 PTD6/ LLWU_P15 ADC0_SE7b 80 64 48 32 PTD7 DISABLED ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 PTD4/ LLWU_P14 SPI1_PCS0 UART2_RX TPM0_CH4 ADC0_SE6b PTD5 SPI1_SCK UART2_TX TPM0_CH5 ADC0_SE7b PTD6/ LLWU_P15 SPI1_MOSI UART0_RX SPI1_MISO PTD7 SPI1_MISO UART0_TX SPI1_MOSI ALT6 ALT7 5.
PAGE 42
PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2 PTD1 PTD0 PTC17 PTC16 PTC13 PTC12 PTC11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Pinout PTB10 PTE20 13 48 PTB9 PTE21 14 47 PTB8 PTE22 15 46 PTB3 PTE23 16 45 PTB2 VDDA 17 44 PTB1 VREFH 18 43 PTB0/LLWU_P5 VREFL 19 42 RESET_b VSSA 20 41 PTA19 40 49 PTA18 12 39 VREGIN VSS PTB11 38 50 VDD 11 37 VOUT33
PAGE 43
PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2 PTD1 PTD0 PTC11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout PTB18 PTE20 9 40 PTB17 PTE21 10 39 PTB16 PTE22 11 38 PTB3 PTE23 12 37 PTB2 VDDA 13 36 PTB1 VREFH 14 35 PTB0/LLWU_P5 VREFL 15 34 RESET_b VSSA 16 33 PTA19 PTA18 32 41 31 8 VSS VREGIN 30 PTB19 VDD 42 29 7 PTA13 VOUT33 28 PTC0 PTA12 43 27 6 PTA5 US
PAGE 44
PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2 PTD1 PTD0 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 48 47 46 45 44 43 42 41 40 39 38 37 Pinout PTB16 PTE20 7 30 PTB3 PTE21 8 29 PTB2 VDDA 9 28 PTB1 VREFH 10 27 PTB0/LLWU_P5 VREFL 11 26 RESET_b VSSA 12 25 PTA19 PTA18 24 31 23 6 VSS VREGIN 22 PTB17 VDD 32 21 5 PTA4 VOUT33 20 PTC0 PTA3 33 19 4 PTA2 USB0_DM 18 PTC1/LLWU_P6/RTC_CLKIN PTA1 34 17 3 PTA0 USB0_DP 16 PTC2 PTE25 35 15
PAGE 45
PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 32 31 30 29 28 27 26 25 Ordering parts 21 PTB1 VOUT33 5 20 PTB0/LLWU_P5 VREGIN 6 19 RESET_b VDDA 7 18 PTA19 VSSA 8 17 PTA18 PTA0 PTE30 16 4 VSS USB0_DM 15 PTC1/LLWU_P6/RTC_CLKIN VDD 22 14 3 PTA4 USB0_DP 13 PTC2 PTA3 23 12 2 PTA2 VSS 11 PTC3/LLWU_P7 PTA1 24 10 1 9 PTE0 Figure 18. KL24 32-pin QFN pinout diagram 6 Ordering parts 6.
PAGE 46
Part identification 7.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 7.2 Format Part numbers for this device have the following format: Q KL## A FFF R T PP CC N 7.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Table 34.
PAGE 47
Terminology and guidelines MKL24Z64VLK4 8 Terminology and guidelines 8.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 8.1.1 Example This is an example of an operating requirement: Symbol VDD Description 1.0 V core supply voltage Min. 0.9 Max. 1.1 Unit V 8.
PAGE 48
Terminology and guidelines 8.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 8.3.1 Example This is an example of an attribute: Symbol CIN_D Description Input capacitance: digital pins Min. — Max. 7 Unit pF 8.
PAGE 49
Terminology and guidelines 8.5 Result of exceeding a rating 40 Failures in time (ppm) 30 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 20 10 0 Operating rating Measured characteristic 8.6 Relationship between ratings and operating requirements g Op g in rat tin era nt ) in. (m me ire era Op g tin .) ) in. (m nt me ire u req g tin era Op ax (m .
PAGE 50
Terminology and guidelines 8.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. 8.8.
PAGE 51
Revision history 5000 4500 4000 TJ IDD_STOP (μA) 3500 150 °C 3000 105 °C 2500 25 °C 2000 –40 °C 1500 1000 500 0 0.90 0.95 1.05 1.00 1.10 VDD (V) 8.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Table 35. Typical value conditions Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V 9 Revision history The following table provides a revision history for this document.
PAGE 52
Revision history Table 36. Revision history Rev. No. Date Substantial Changes • • • • • • • • • • • • 52 Freescale Semiconductor, Inc.
PAGE 53
How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein.