Datasheet

Table 18. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
Δf
dco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
— +0.5/-0.7 ± 3 %f
dco
1, 2
Δf
dco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70 °C
— ± 0.4 ± 1.5 %f
dco
1, 2
f
intf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal V
DD
and 25 °C
— 4 — MHz
Δf
intf_ft
Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal V
DD
and 25 °C
— +1/-2 ± 3 %f
intf_ft
2
f
intf_t
Internal reference frequency (fast clock) — user
trimmed at nominal V
DD
and 25 °C
3 — 5 MHz
f
loc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
f
ints_t
— — kHz
f
loc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
f
ints_t
— — kHz
FLL
f
fll_ref
FLL reference frequency range 31.25 — 39.0625 kHz
f
dco
DCO output
frequency range
Low range (DRS = 00)
640 × f
fll_ref
20 20.97 25 MHz 3, 4
Mid range (DRS = 01)
1280 × f
fll_ref
40 41.94 48 MHz
f
dco_t_DMX3
2
DCO output
frequency
Low range (DRS = 00)
732 × f
fll_ref
— 23.99 — MHz 5, 6
Mid range (DRS = 01)
1464 × f
fll_ref
— 47.97 — MHz
J
cyc_fll
FLL period jitter
• f
VCO
= 48 MHz
— 180 — ps 7
t
fll_acquire
FLL target frequency acquisition time — — 1 ms 8
PLL
f
vco
VCO operating frequency 48.0 — 100 MHz
I
pll
PLL operating current
• PLL at 96 MHz (f
osc_hi_1
= 8 MHz, f
pll_ref
=
2 MHz, VDIV multiplier = 48)
— 1060 — µA
9
I
pll
PLL operating current
• PLL at 48 MHz (f
osc_hi_1
= 8 MHz, f
pll_ref
=
2 MHz, VDIV multiplier = 24)
— 600 — µA
9
f
pll_ref
PLL reference frequency range 2.0 — 4.0 MHz
J
cyc_pll
PLL period jitter (RMS)
• f
vco
= 48 MHz
• f
vco
= 100 MHz
—
—
120
50
—
—
ps
ps
10
Table continues on the next page...
Peripheral operating requirements and behaviors
Kinetis KL24 Sub-Family, Rev4 03/2014. 21
Freescale Semiconductor, Inc.