Datasheet

Table 18. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
J
acc_pll
PLL accumulated jitter over 1µs (RMS)
• f
vco
= 48 MHz
• f
vco
= 100 MHz
—
—
1350
600
—
—
ps
ps
10
D
lock
Lock entry frequency tolerance ± 1.49 — ± 2.98 %
D
unl
Lock exit frequency tolerance ± 4.47 — ± 5.97 %
t
pll_lock
Lock detector detection time — — 150 × 10
-6
+ 1075(1/
f
pll_ref
)
s 11
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. The deviation is relative to the factory trimmed frequency at nominal V
DD
and 25 °C, f
ints_ft
.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.
4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation
(Δf
dco_t
) over voltage and temperature must be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
9. Excludes any oscillator currents that are also consuming power while PLL is in operation.
10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics
of each PCB and results will vary.
11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
3.3.2 Oscillator electrical specifications
3.3.2.1 Oscillator DC electrical specifications
Table 19. Oscillator DC electrical specifications
Symbol Description Min. Typ. Max. Unit Notes
V
DD
Supply voltage 1.71 — 3.6 V
I
DDOSC
Supply current — low-power mode (HGO=0)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
nA
μA
μA
μA
mA
1
Table continues on the next page...
Peripheral operating requirements and behaviors
22 Kinetis KL24 Sub-Family, Rev4 03/2014.
Freescale Semiconductor, Inc.