Datasheet

Table 27. Comparator and 6-bit DAC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
— 30 — mV
V
CMPOh
Output high V
DD
– 0.5 — — V
V
CMPOl
Output low — — 0.5 V
t
DHS
Propagation delay, high-speed mode (EN = 1,
PMODE = 1)
20 50 200 ns
t
DLS
Propagation delay, low-speed mode (EN = 1,
PMODE = 0)
80 250 600 ns
Analog comparator initialization delay
2
— — 40 μs
I
DAC6b
6-bit DAC current adder (enabled) — 7 — μA
INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB
3
DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB
1. Typical hysteresis is measured with input voltage range limited to 0.7 to V
DD
– 0.7 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to
DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = V
reference
/64
40.00E-03
50.00E-03
60.00E-03
70.00E-03
80.00E-03
90.00E-03
CMP Hysteresis (V)
CMP Hysteresis vs Vinn
0
1
2
HYSTCTR
Setting
000.00E+00
10.00E-03
20.00E-03
30.00E-03
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
CMP Hysteresis (V)
Vinn (V)
3
Figure 8. Typical hysteresis vs. Vin level (V
DD
= 3.3 V, PMODE = 0)
Peripheral operating requirements and behaviors
30 Kinetis KL24 Sub-Family, Rev4 03/2014.
Freescale Semiconductor, Inc.