Datasheet

Table 29. SPI master mode timing on slew rate disabled pads (continued)
Num. Symbol Description Min. Max. Unit Note
5 t
WSPSCK
Clock (SPSCK) high or low time t
periph
– 30 1024 x
t
periph
ns —
6 t
SU
Data setup time (inputs) 16 — ns —
7 t
HI
Data hold time (inputs) 0 — ns —
8 t
v
Data valid (after SPSCK edge) — 10 ns —
9 t
HO
Data hold time (outputs) 0 — ns —
10 t
RI
Rise time input — t
periph
– 25 ns —
t
FI
Fall time input
11 t
RO
Rise time output — 25 ns —
t
FO
Fall time output
1. For SPI0, f
periph
is the bus clock (f
BUS
). For SPI1 f
periph
is the system clock (f
SYS
).
2. t
periph
= 1/f
periph
Table 30. SPI master mode timing on slew rate enabled pads
Num. Symbol Description Min. Max. Unit Note
1 f
op
Frequency of operation f
periph
/2048 f
periph
/2 Hz 1
2 t
SPSCK
SPSCK period 2 x t
periph
2048 x
t
periph
ns 2
3 t
Lead
Enable lead time 1/2 — t
SPSCK
—
4 t
Lag
Enable lag time 1/2 — t
SPSCK
—
5 t
WSPSCK
Clock (SPSCK) high or low time t
periph
– 30 1024 x
t
periph
ns —
6 t
SU
Data setup time (inputs) 96 — ns —
7 t
HI
Data hold time (inputs) 0 — ns —
8 t
v
Data valid (after SPSCK edge) — 52 ns —
9 t
HO
Data hold time (outputs) 0 — ns —
10 t
RI
Rise time input — t
periph
– 25 ns —
t
FI
Fall time input
11 t
RO
Rise time output — 36 ns —
t
FO
Fall time output
1. For SPI0, f
periph
is the bus clock (f
BUS
). For SPI1 f
periph
is the system clock (f
SYS
).
2. t
periph
= 1/f
periph
Peripheral operating requirements and behaviors
Kinetis KL24 Sub-Family, Rev4 03/2014. 33
Freescale Semiconductor, Inc.