Datasheet

(OUTPUT)
2
8
6 7
MSB IN
2
LSB IN
MSB OUT
2
LSB OUT
9
5
5
3
(CPOL=0)
4
11
11
10
10
SPSCK
SPSCK
(CPOL=1)
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1. If configured as an output.
SS
1
(OUTPUT)
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT)
BIT 6 . . . 1
BIT 6 . . . 1
Figure 10. SPI master mode timing (CPHA = 0)
<<CLASSIFICATION>>
<<NDA MESSAGE>>
38
2
6 7
MSB IN
2
BIT 6 . . . 1
MASTER MSB OUT
2
MASTER LSB OUT
5
5
8
10 11
PORT DATA
PORT DATA
3
10 11 4
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
9
(OUTPUT)
(CPOL=0)
SPSCK
SPSCK
(CPOL=1)
SS
1
(OUTPUT)
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT)
LSB IN
BIT 6 . . . 1
Figure 11. SPI master mode timing (CPHA = 1)
Table 31. SPI slave mode timing on slew rate disabled pads
Num. Symbol Description Min. Max. Unit Note
1 f
op
Frequency of operation 0 f
periph
/4 Hz 1
2 t
SPSCK
SPSCK period 4 x t
periph
— ns 2
3 t
Lead
Enable lead time 1 — t
periph
—
Table continues on the next page...
Peripheral operating requirements and behaviors
34 Kinetis KL24 Sub-Family, Rev4 03/2014.
Freescale Semiconductor, Inc.