Datasheet

3.8.4 Inter-Integrated Circuit Interface (I2C) timing
Table 33. I2C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency f
SCL
0 100 0 400
1
kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
t
HD
; STA 4 — 0.6 — µs
LOW period of the SCL clock t
LOW
4.7 — 1.3 — µs
HIGH period of the SCL clock t
HIGH
4 — 0.6 — µs
Set-up time for a repeated START
condition
t
SU
; STA 4.7 — 0.6 — µs
Data hold time for I
2
C bus devices t
HD
; DAT 0
2
3.45
3
0
4
0.9
2
µs
Data set-up time t
SU
; DAT 250
5
— 100
3
,
6
— ns
Rise time of SDA and SCL signals t
r
— 1000 20 +0.1C
b
7
300 ns
Fall time of SDA and SCL signals t
f
— 300 20 +0.1C
b
6
300 ns
Set-up time for STOP condition t
SU
; STO 4 — 0.6 — µs
Bus free time between STOP and
START condition
t
BUF
4.7 — 1.3 — µs
Pulse width of spikes that must be
suppressed by the input filter
t
SP
N/A N/A 0 50 ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only achieved when using the High
drive pins (see Voltage and current operating behaviors) or when using the Normal drive pins and VDD ≥ 2.7 V
2. The master mode I
2
C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and
SCL lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I
2
C bus device can be used in a Standard mode I2C bus system, but the requirement t
SU; DAT
≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t
rmax
+ t
SU; DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I
2
C bus specification) before the SCL line is
released.
7. C
b
= total capacitance of the one bus line in pF.


SDA
SCL
t
HD; STA
t
HD; DAT
t
LOW
t
SU; DAT
t
HIGH
t
SU; STA
SR
P
S
S
t
HD; STA
t
SP
t
SU; STO
t
BUF
t
f
t
r
t
f
t
r
Figure 14. Timing definition for fast and standard mode devices on the I
2
C bus
Peripheral operating requirements and behaviors
Kinetis KL24 Sub-Family, Rev4 03/2014. 37
Freescale Semiconductor, Inc.