Datasheet

Table 8. Power mode transition operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit
instruction across the operating temperature
range of the chip.
• VLLS0 → RUN
— 95 115 μs
• VLLS1 → RUN
— 93 115 μs
• VLLS3 → RUN
— 42 53 μs
• LLS → RUN
— 4 4.6 μs
• VLPS → RUN
— 4 4.4 μs
• STOP → RUN
— 4 4.4 μs
1. Normal boot (FTFA_FOPT[LPBOOT]=11).
2.2.5 Power consumption operating behaviors
Table 9. Power consumption operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
I
DDA
Analog supply current — — See note mA 1
I
DD_RUNCO
_CM
Run mode current in compute operation - 48
MHz core / 24 MHz flash / bus disabled,
LPTMR running using 4 MHz internal reference
clock, CoreMark® benchmark code executing
from flash
• at 3.0 V
— 6.4 — mA
2
I
DD_RUNCO
Run mode current in compute operation - 48
MHz core / 24 MHz flash / bus clock disabled,
code of while(1) loop executing from flash
• at 3.0 V
— 4.1 5.2 mA
3
I
DD_RUN
Run mode current - 48 MHz core / 24 MHz bus
and flash, all peripheral clocks disabled, code
of while(1) loop executing from flash
• at 3.0 V
— 5.1 6.3 mA
3
I
DD_RUN
Run mode current - 48 MHz core / 24 MHz bus
and flash, all peripheral clocks enabled, code of
while(1) loop executing from flash
— 6.4 7.8 mA
3, 4
Table continues on the next page...
General
Kinetis KL24 Sub-Family, Rev4 03/2014. 9
Freescale Semiconductor, Inc.