Datasheet

Table 25. 16-bit ADC operating conditions (continued)
Symbol Description Conditions Min. Typ.
1
Max. Unit Notes
V
ADIN
Input voltage • 16-bit differential mode
• All other modes
VREFL
VREFL
—
—
31/32 *
VREFH
VREFH
V
C
ADIN
Input
capacitance
• 16-bit mode
• 8-bit / 10-bit / 12-bit
modes
—
—
8
4
10
5
pF
R
ADIN
Input series
resistance
— 2 5 kΩ
R
AS
Analog source
resistance
(external)
13-bit / 12-bit modes
f
ADCK
< 4 MHz — — 5 kΩ
4
f
ADCK
ADC conversion
clock frequency
≤ 13-bit mode 1.0 — 18.0 MHz 5
f
ADCK
ADC conversion
clock frequency
16-bit mode 2.0 — 12.0 MHz 5
C
rate
ADC conversion
rate
≤ 13-bit modes
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
20.000 — 818.330 Ksps
6
C
rate
ADC conversion
rate
16-bit mode
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
37.037 — 461.467 Ksps
6
1. Typical values assume V
DDA
= 3.0 V, Temp = 25 °C, f
ADCK
= 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. For packages without dedicated VREFH and VREFL pins, V
REFH
is internally tied to V
DDA
, and V
REFL
is internally tied
to V
SSA
.
4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The R
AS
/
C
AS
time constant should be kept to < 1 ns.
5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
Peripheral operating requirements and behaviors
Kinetis KL25 Sub-Family, Rev4 03/2014. 27
Freescale Semiconductor, Inc.