Datasheet

5 Pinout
5.1 KL25 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
80
LQFP
64
LQFP
48
QFN
32
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
1 1 — 1 PTE0 DISABLED PTE0 UART1_TX RTC_
CLKOUT
CMP0_OUT I2C1_SDA
2 2 — — PTE1 DISABLED PTE1 SPI1_MOSI UART1_RX SPI1_MISO I2C1_SCL
3 — — — PTE2 DISABLED PTE2 SPI1_SCK
4 — — — PTE3 DISABLED PTE3 SPI1_MISO SPI1_MOSI
5 — — — PTE4 DISABLED PTE4 SPI1_PCS0
6 — — — PTE5 DISABLED PTE5
7 3 1 — VDD VDD VDD
8 4 2 2 VSS VSS VSS
9 5 3 3 USB0_DP USB0_DP USB0_DP
10 6 4 4 USB0_DM USB0_DM USB0_DM
11 7 5 5 VOUT33 VOUT33 VOUT33
12 8 6 6 VREGIN VREGIN VREGIN
13 9 7 — PTE20 ADC0_DP0/
ADC0_SE0
ADC0_DP0/
ADC0_SE0
PTE20 TPM1_CH0 UART0_TX
14 10 8 — PTE21 ADC0_DM0/
ADC0_SE4a
ADC0_DM0/
ADC0_SE4a
PTE21 TPM1_CH1 UART0_RX
15 11 — — PTE22 ADC0_DP3/
ADC0_SE3
ADC0_DP3/
ADC0_SE3
PTE22 TPM2_CH0 UART2_TX
16 12 — — PTE23 ADC0_DM3/
ADC0_SE7a
ADC0_DM3/
ADC0_SE7a
PTE23 TPM2_CH1 UART2_RX
17 13 9 7 VDDA VDDA VDDA
18 14 10 — VREFH VREFH VREFH
19 15 11 — VREFL VREFL VREFL
20 16 12 8 VSSA VSSA VSSA
21 17 13 — PTE29 CMP0_IN5/
ADC0_SE4b
CMP0_IN5/
ADC0_SE4b
PTE29 TPM0_CH2 TPM_CLKIN0
22 18 14 9 PTE30 DAC0_OUT/
ADC0_SE23/
CMP0_IN4
DAC0_OUT/
ADC0_SE23/
CMP0_IN4
PTE30 TPM0_CH3 TPM_CLKIN1
23 19 — — PTE31 DISABLED PTE31 TPM0_CH4
Pinout
Kinetis KL25 Sub-Family, Rev4 03/2014. 43
Freescale Semiconductor, Inc.