Datasheet

80
LQFP
64
LQFP
48
QFN
32
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
24 20 15 PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL
25 21 16 PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA
26 22 17 10 PTA0 SWD_CLK TSI0_CH1 PTA0 TPM0_CH5 SWD_CLK
27 23 18 11 PTA1 DISABLED TSI0_CH2 PTA1 UART0_RX TPM2_CH0
28 24 19 12 PTA2 DISABLED TSI0_CH3 PTA2 UART0_TX TPM2_CH1
29 25 20 13 PTA3 SWD_DIO TSI0_CH4 PTA3 I2C1_SCL TPM0_CH0 SWD_DIO
30 26 21 14 PTA4 NMI_b TSI0_CH5 PTA4 I2C1_SDA TPM0_CH1 NMI_b
31 27 PTA5 DISABLED PTA5 USB_CLKIN TPM0_CH2
32 28 PTA12 DISABLED PTA12 TPM1_CH0
33 29 PTA13 DISABLED PTA13 TPM1_CH1
34 PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX
35 PTA15 DISABLED PTA15 SPI0_SCK UART0_RX
36 PTA16 DISABLED PTA16 SPI0_MOSI SPI0_MISO
37 PTA17 DISABLED PTA17 SPI0_MISO SPI0_MOSI
38 30 22 15 VDD VDD VDD
39 31 23 16 VSS VSS VSS
40 32 24 17 PTA18 EXTAL0 EXTAL0 PTA18 UART1_RX TPM_CLKIN0
41 33 25 18 PTA19 XTAL0 XTAL0 PTA19 UART1_TX TPM_CLKIN1 LPTMR0_
ALT1
42 34 26 19 PTA20 RESET_b PTA20 RESET_b
43 35 27 20 PTB0/
LLWU_P5
ADC0_SE8/
TSI0_CH0
ADC0_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL TPM1_CH0
44 36 28 21 PTB1 ADC0_SE9/
TSI0_CH6
ADC0_SE9/
TSI0_CH6
PTB1 I2C0_SDA TPM1_CH1
45 37 29 PTB2 ADC0_SE12/
TSI0_CH7
ADC0_SE12/
TSI0_CH7
PTB2 I2C0_SCL TPM2_CH0
46 38 30 PTB3 ADC0_SE13/
TSI0_CH8
ADC0_SE13/
TSI0_CH8
PTB3 I2C0_SDA TPM2_CH1
47 PTB8 DISABLED PTB8 EXTRG_IN
48 PTB9 DISABLED PTB9
49 PTB10 DISABLED PTB10 SPI1_PCS0
50 PTB11 DISABLED PTB11 SPI1_SCK
51 39 31 PTB16 TSI0_CH9 TSI0_CH9 PTB16 SPI1_MOSI UART0_RX TPM_CLKIN0 SPI1_MISO
52 40 32 PTB17 TSI0_CH10 TSI0_CH10 PTB17 SPI1_MISO UART0_TX TPM_CLKIN1 SPI1_MOSI
53 41 PTB18 TSI0_CH11 TSI0_CH11 PTB18 TPM2_CH0
54 42 PTB19 TSI0_CH12 TSI0_CH12 PTB19 TPM2_CH1
55 43 33 PTC0 ADC0_SE14/
TSI0_CH13
ADC0_SE14/
TSI0_CH13
PTC0 EXTRG_IN CMP0_OUT
56 44 34 22 PTC1/
LLWU_P6/
RTC_CLKIN
ADC0_SE15/
TSI0_CH14
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6/
RTC_CLKIN
I2C1_SCL TPM0_CH0
Pinout
44 Kinetis KL25 Sub-Family, Rev4 03/2014.
Freescale Semiconductor, Inc.