Datasheet

80
LQFP
64
LQFP
48
QFN
32
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
57 45 35 23 PTC2 ADC0_SE11/
TSI0_CH15
ADC0_SE11/
TSI0_CH15
PTC2 I2C1_SDA TPM0_CH1
58 46 36 24 PTC3/
LLWU_P7
DISABLED PTC3/
LLWU_P7
UART1_RX TPM0_CH2 CLKOUT
59 47 — — VSS VSS VSS
60 48 — — VDD VDD VDD
61 49 37 25 PTC4/
LLWU_P8
DISABLED PTC4/
LLWU_P8
SPI0_PCS0 UART1_TX TPM0_CH3
62 50 38 26 PTC5/
LLWU_P9
DISABLED PTC5/
LLWU_P9
SPI0_SCK LPTMR0_
ALT2
CMP0_OUT
63 51 39 27 PTC6/
LLWU_P10
CMP0_IN0 CMP0_IN0 PTC6/
LLWU_P10
SPI0_MOSI EXTRG_IN SPI0_MISO
64 52 40 28 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_MISO SPI0_MOSI
65 53 — — PTC8 CMP0_IN2 CMP0_IN2 PTC8 I2C0_SCL TPM0_CH4
66 54 — — PTC9 CMP0_IN3 CMP0_IN3 PTC9 I2C0_SDA TPM0_CH5
67 55 — — PTC10 DISABLED PTC10 I2C1_SCL
68 56 — — PTC11 DISABLED PTC11 I2C1_SDA
69 — — — PTC12 DISABLED PTC12 TPM_CLKIN0
70 — — — PTC13 DISABLED PTC13 TPM_CLKIN1
71 — — — PTC16 DISABLED PTC16
72 — — — PTC17 DISABLED PTC17
73 57 41 — PTD0 DISABLED PTD0 SPI0_PCS0 TPM0_CH0
74 58 42 — PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK TPM0_CH1
75 59 43 — PTD2 DISABLED PTD2 SPI0_MOSI UART2_RX TPM0_CH2 SPI0_MISO
76 60 44 — PTD3 DISABLED PTD3 SPI0_MISO UART2_TX TPM0_CH3 SPI0_MOSI
77 61 45 29 PTD4/
LLWU_P14
DISABLED PTD4/
LLWU_P14
SPI1_PCS0 UART2_RX TPM0_CH4
78 62 46 30 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI1_SCK UART2_TX TPM0_CH5
79 63 47 31 PTD6/
LLWU_P15
ADC0_SE7b ADC0_SE7b PTD6/
LLWU_P15
SPI1_MOSI UART0_RX SPI1_MISO
80 64 48 32 PTD7 DISABLED PTD7 SPI1_MISO UART0_TX SPI1_MOSI
5.2 KL25 pinouts
The following figures show the pinout diagrams for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see KL25 Signal Multiplexing and Pin
Assignments.
Pinout
Kinetis KL25 Sub-Family, Rev4 03/2014. 45
Freescale Semiconductor, Inc.