Datasheet

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Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MPC5121E

Rev. 5, 02/2012

MPC5121E/MPC5123

516 TEPBGA

27 mm x 27 mm

The MPC5121e/MPC5123 integrates a high performance

e300 CPU core based on the Power Architecture

Technology

with a rich set of peripheral functions focused on

communications and systems integration.

Major features of the MPC5121e/MPC5123 are:

• e300 Power Architecture processor core

• Power modes include doze, nap, sleep, deep sleep, and

hibernate

• AXE – Auxiliary Execution Engine

• MBX Lite – 2D/3D graphics engine (not available in

MPC5123)

• DIU – Display interface unit

• DDR1, DDR2, and LPDDR/mobile-DDR SDRAM

memory controller

• MEM – 128 KB on-chip SRAM

• USB 2.0 OTG controller with integrated physical layer

(PHY)

• DMA subsystem

• EMB – Flexible multi-function external memory bus

interface

• NFC – NAND flash controller

• LPC – LocalPlus interface

• 10/100Base Ethernet

• PCI interface, version 2.3

• PATA – Parallel ATA integrated development environment

(IDE) controller

• SATA – Serial ATA controller with integrated physical

layer (PHY)

• SDHC – MMC/SD/SDIO card host controller

• PSC – Programmable serial controller

•I

C – inter-integrated circuit communication interfaces

• S/PDIF – Serial audio interface

• CAN – Controller area network

• BDLC – J1850 interface

• VIU – Video Input, ITU-656 compliant

• RTC – On-Chip real-time clock

• On-chip temperature sensor

• IIM – IC Identification module

MPC5121E/MPC5123 

Data Sheet

Summary of content (88 pages)

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Freescale Semiconductor Data Sheet: Technical Data Document Number: MPC5121E Rev. 5, 02/2012 MPC5121E/MPC5123 MPC5121E/MPC5123  Data Sheet The MPC5121e/MPC5123 integrates a high performance e300 CPU core based on the Power Architecture® Technology with a rich set of peripheral functions focused on communications and systems integration.
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Table of Contents 1 2 3 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.1 516-TEPBGA Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.2 Pinout Listings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Electrical and Thermal Characteristics . . . . . . . . . . . . . . . . . .17 3.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . .
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Ordering Information Figure 1 shows a simplified MPC5121e/MPC5123 block diagram.
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Ordering Information Table 2. MPC5123 Orderable Part Numbers (continued) Freescale Part Number Speed (MHz) Temperature (ambient) Qualification Package Availability MPC5123YVY400BR 400 –40 oC to 85 oC SPC5123YVY400B SPC5123YVY400BR 400 400 Industrial RoHS and Pb-free Tape and Reel o o Automotive—AEC RoHS and Pb-free Tray o o Automotive—AEC RoHS and Pb-free Tape and Reel –40 C to 85 C –40 C to 85 C MPC5121E/MPC5123 Data Sheet, Rev.
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Pin Assignments 2 Pin Assignments This section details pin assignments. 2.
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Pin Assignments 2.2 Pinout Listings Table 3 provides the pin-out listing for the MPC5121e/MPC5123. Table 3.
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Pin Assignments Table 3.
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Pin Assignments Table 3.
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Pin Assignments Table 3.
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Pin Assignments Table 3.
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Pin Assignments Table 3.
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Pin Assignments Table 3.
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Pin Assignments Table 3.
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Pin Assignments Table 3.
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Pin Assignments Table 3.
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Pin Assignments Table 3.
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Pin Assignments Table 3.
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Electrical and Thermal Characteristics 3 Electrical and Thermal Characteristics 3.1 DC Electrical Characteristics 3.1.1 Absolute Maximum Ratings The tables in this section describe the MPC5121e/MPC5123 DC Electrical characteristics. Table 4 gives the absolute maximum ratings. Table 4. Absolute Maximum Ratings1 Characteristic Symbol Min Max Unit SpecID VDD_CORE –0.3 1.47 V D1.1 VDD_IO, VDD_MEM_IO –0.3 3.6 V D1.2 MVREF –0.3 3.6 V MVTT –0.3 3.6 V SYS_PLL_AVDD –0.3 3.6 V D1.
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Electrical and Thermal Characteristics 3.1.2 Recommended Operating Conditions Table 5 gives the recommended operating conditions. 3) Table 5. Recommended Operating Conditions Characteristic Supply voltage – e300 core and peripheral logic Symbol Min1 Typ Max1 VDD_CORE 1.33 1.4 1.47 — — State Retention voltage – e300 core and peripheral logic 2 1.08 Supply voltage – standard I / O buffers Unit SpecID V D2.1 V D2.2 VDD_IO 3.0 3.3 3.6 V D2.
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Electrical and Thermal Characteristics 3.1.3 DC Electrical Specifications Table 6 gives the DC Electrical characteristics for the MPC5121e/MPC5123 at recommended operating conditions. Table 6. DC Electrical Specifications Characteristic Condition Symbol Min Max Unit SpecID Input high voltage Input type = TTL VDD_IO VIH 0.51 × VDD_IO — V D3.1 Input high voltage Input type = TTL VDD_MEM_IO_DDR VIH MVREF + 0.15 — V D3.
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Electrical and Thermal Characteristics Table 6. DC Electrical Specifications (continued) Characteristic Condition Input leakage current RTC_XTALI Vin = 0 or VDD_IO Symbol Min Max Unit SpecID IIN — 1.0 µA D3.23 Input current, pullup resistor6 Pullup VDD_IO Vin = VIL IINpu 25 150 µA D3.24 Input current, pulldown resistor 8 Pulldown VDD_IO Vin = VIH IINpd 25 150 µA D3.25 Output high voltage IOH is driver dependent7 VDD_IO VOH 0.8 × VDD_IO — V D3.26 V D3.27 V D3.
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Electrical and Thermal Characteristics 7 See Table 7 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin as listed in Table 3. 8 All injection current is transferred to VDD_IO/VDD_MEM_IO. An external load is required to dissipate this current to maintain the power supply within the specified voltage range. Total injection current for all digital input-only and all digital input/output pins must not exceed 10 mA.
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Electrical and Thermal Characteristics 3.1.4 Electrostatic Discharge CAUTION This device contains circuitry that protects against damage due to high-static voltage or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages. Operational reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (GND or VDD ). Table 10 gives package thermal characteristics for this device. Table 8.
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Electrical and Thermal Characteristics Table 9. Power Dissipation (continued) Core Power Supply (VDD_CORE) SpecID High-Performance Mode Unit e300 = 300 MHz, CSB = 200 MHz Typical 300 mW D5.5 PHY Power Supplies (USB_VDDA, SATA_VDDA) Typical 1 200 mW D5.6 Typical core power is measured at VDD_CORE = 1.4 V, Tj = 25 oC. NOTE The maximum power depends on the supply voltage, process corner, junction temperature, and the concrete application and clock configurations.
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Electrical and Thermal Characteristics 3.1.6.1 Heat Dissipation An estimation of the chip-junction temperature, TJ, can be obtained from the following equation: TJ = TA + ( R JA  PD ) Eqn. 3 where: TA = ambient temperature for the package ( º C ) R JA = junction to ambient thermal resistance ( º C / W ) PD = power dissipation in package ( W ) The junction to ambient thermal resistance is an industry standard value, which provides a quick and easy estimation of thermal performance.
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Electrical and Thermal Characteristics from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 3.2 Oscillator and PLL Electrical Characteristics The MPC5121e/MPC5123 System requires a system-level clock input SYS_XTALI. This clock input may be driven directly from an external oscillator or with a crystal using the internal oscillator.
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Electrical and Thermal Characteristics 4 5 Fall time is measured from 20% of vdd to 80% of VDD. SYS_XTALI duty cycle is measured at V M. 3.2.2 RTC Oscillator Electrical Characteristics Table 13. RTC Oscillator Electrical Characteristics Characteristic RTC_XTALI frequency 3.2.3 Symbol Min Typical Max Unit SpecID frtc_xtal — 32.768 — kHz O2.1 System PLL Electrical Characteristics Table 14. System PLL Specifications Characteristic Symbol Min Typical Max Unit SpecID fsys_xtal 16 33.
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Electrical and Thermal Characteristics 1 The frequency and e300 PLL Configuration bits must be chosen such that the resulting system frequencies, CPU (core) frequency, and e300 PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies in Table 16. There is a hard coded relationship between fcore and fVCOcore (fcore = fVCOcore/2).
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Electrical and Thermal Characteristics 3.3 AC Electrical Characteristics 3.3.1 Overview Hyperlinks to the indicated timing specification sections are provided in the following: • AC Operating Frequency Data • SDHC • Resets • DIU • External Interrupts • SPDIF • SDRAM (DDR) • CAN • PCI • I2C • LPC • J1850 • NFC • PSC • PATA • GPIOs and Timers • SATA PHY • Fusebox • FEC • IEEE 1149.
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Electrical and Thermal Characteristics Table 16. Clock Frequencies (continued) Min Max Units SpecID NFC Clock 2.08 83 MHz A1.7 DIU Clock 0.78 100 MHz A1.8 SDHC Clock 0.78 66.6 MHz A1.9 MBX Clock 6.25 100 MHz A1.10 NOTES: 1. The SYS_XTALI frequency, Sys PLL, and CORE PLL settings must be chosen so that the resulting e300 clk, csb_clk, MCK, frequencies do not exceed their respective maximum or minimum operating frequencies. 2. The values are valid for the user operation mode.
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Electrical and Thermal Characteristics SYS_XTALI PORESET tHRVAL HRESET tSRVAL SRESET tS_POR_CONF tEXEC RST_CONF[31:0] ADDR[31:0] tH_POR_CONF Figure 4. Power-Up Behavior SYS_XTALI tPORHold PORESET tHRVAL HRESET tSRVAL SRESET tS_POR_CONF tEXEC RST_CONF[31:0] ADDR[31:0] tH_POR_CONF Figure 5. Power-On Reset Behavior MPC5121E/MPC5123 Data Sheet, Rev.
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Electrical and Thermal Characteristics SYS_XTALI PORESET tHRHOLD tHRVAL HRESET tSRVAL SRESET tHR_SR_Delay tEXEC RST_CONF[31:0] ADDR[31:0] no new fetch of the RST_CONF Figure 6. HRESET Behavior SYS_XTALI PORESET tSRHOLD HRESET tSRMIN SRESET tEXEC RST_CONF[31:0] ADDR[31:0] no new fetch of the RST_CONF Figure 7. SRESET Behavior Table 18. Reset Timing Symbol tPORHOLD Description Time PORESET must be held low before a qualified reset occurs Value SYS_XTALI SpecID 4 cycles A3.
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Electrical and Thermal Characteristics Table 18. Reset Timing (continued) Symbol Description Value SYS_XTALI SpecID tS_POR_CONF Reset configuration setup time before assertion of PORESET 1 cycle A3.14 tH_POR_CONF Reset configuration hold time after assertion of PORESET 1 cycle A3.15 tHR_SR_DELAY Time from falling edge of HRESET to falling edge of SRESET 4 cycles A3.16 tHRHOLD Time HRESET must be held low before a qualified reset occurs 4 cycles A3.
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Electrical and Thermal Characteristics 3.3.5.1 DDR and DDR2 SDRAM AC Timing Specifications Table 20. DDR and DDR2 (DDR2-400) SDRAM Timing Specifications At recommended operating conditions with VDD_MEM_IO of 5% Parameter Symbol Min Max Unit Clock cycle time, CL=x tCK 5000 — ps CK HIGH pulse width tCH 0.47 0.53 tCK 12 , A5.3 tCK 12 , A5.4 CK LOW pulse width SpecID A5.1 tCL 0.47 tDQSS 0.25 0.25 tCK 2 3 , A5.
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Electrical and Thermal Characteristics DQS(in) Any DQ(in) tDQSQ tDQSQ Figure 9. DDR Read Timing, DQ vs DQS Command Read Address tOS tOH DQS (in) tDQSEN (min) tDQSEN Figure 10. DDR Read Timing, DQSEN Figure 11 provides the AC test load for the DDR bus. Output Z0 = 50  RL = 50  VDD_MEM_IO/2 Figure 11. DDR AC Test Load 3.3.6 PCI The PCI interface on the MPC5121e/MPC5123 is designed to PCI Version 2.3 and supports 33 and 66 MHz PCI operations.
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Electrical and Thermal Characteristics t cyc t high t low 0.6Vcc PCI CLK 0.5Vcc 0.4Vcc 0.3Vcc 0.4Vcc, p-to-p (minimum) 0.2Vcc Figure 12. PCI CLK Waveform 2 Table 21. PCI CLK Specifications 66 MHz1 Sym Description 33 MHz Units SpecID Min2 Max Min Max tcyc PCI CLK Cycle Time1,3 15 30 30 — ns A6.1 thigh PCI CLK High Time 6 — 11 — ns A6.2 t low PCI CLK Low Time 6 — 11 — ns A6.3 1.5 4 1 4 V/ns A6.
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Electrical and Thermal Characteristics 4 See the timing measurement conditions in the PCI Local Bus Specification. For Measurement and Test Conditions, see the PCI Local Bus Specification. 3.3.7 LPC The Local Plus Bus is the external bus interface of the MPC5121e/MPC5123. A maximum of eight configurable chip selects (CS) are provided. There are two main modes of operation: non-MUXed and MUXED. The reference clock is the LPC CLK. The maximum bus frequency is 83 MHz.
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Electrical and Thermal Characteristics Table 23. LPC Timing (continued) Sym Description Min Max Units SpecID (2.5 + WS) × tLPCck – tOD (2.5 + WS) × tLPCck + tOD ns A7.15 tLPCck – tOD — ns A7.16 0.5 × tLPCck – tOD 0.5 × tLPCck + tOD ns A7.17 AL × 2 × tLPCck – tOD AL × 2 × tLPCck ns A7.
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Electrical and Thermal Characteristics 3.3.7.1 Non-MUXed Mode 3.3.7.1.1 Non-MUXed Non-Burst Mode tLPCck LPC CLK t1 CS[x] ADDR t2 t3 t4 OE R/W DATA (wr) t6 t7 DATA (rd) ACK t5 TS TSIZ[1:0] Figure 13. Timing Diagram – Non-MUXed Non-Burst Mode NOTE ACK is asynchonous input signal and has no timing requirements. ACK needs to be deasserted after CS[x] is deasserted. MPC5121E/MPC5123 Data Sheet, Rev.
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Electrical and Thermal Characteristics 3.3.7.1.2 Non-MUXed Synchronous Read Burst Mode LPC_CLK t8 CS[x] t2 t4 Valid Address ADDR t5 TS t3 OE R/W t10 t6 t7 DATA (rd) t11 t9 ACK Figure 14. Timing Diagram – Non-MUXed Synchronous Read Burst Mode 3.3.7.1.3 Non-MUXed Synchronous Write Burst Mode LPC_CLK t12 CS[x] t2 t13 Valid Address ADDR t5 TS R/W t15 t15 DATA (wr) t9 ACK t14 Figure 15. Timing Diagram – Non-MUXed Synchronous Write Burst MPC5121E/MPC5123 Data Sheet, Rev.
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Electrical and Thermal Characteristics 3.3.7.1.4 Non-MUXed Asynchronous Read Burst Mode (Page Mode) LPC_CLK t8 CS[x] t2 t4 Valid Address (Page address) ADDR[31:n+1] t19 Valid Address ADDR[n:0] Valid Address t5 TS t3 OE t20 t6 R/W t21 t10 t7 DATA (rd) t11 t9 ACK Figure 16. Timing Diagram – Non-MUXed Asynchronous Read Burst 3.3.7.1.
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Electrical and Thermal Characteristics 3.3.7.2 MUXed Mode 3.3.7.2.1 MUXed Non-Burst Mode LPC_CLK t17 AD[31:0] (wr) Address Valid Write Data t6 AD[31:0] (rd) t7 Address t4 R/W t18 ALE t5 TS t22 CS[x] t3 OE ACK TSIZ[1:0] Figure 18. Timing Diagram – MUXed Non-Burst Mode NOTE ACK is asynchonous input signal and has no timing requirements. ACK needs to be deasserted after CS[x] is deasserted. MPC5121E/MPC5123 Data Sheet, Rev.
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Electrical and Thermal Characteristics 3.3.7.2.2 MUXed Synchronous Read Burst Mode LPC_CLK t6 t17 AD[31:0] (rd) t10 t7 Address t18 ALE t5 TS t23 CSx t3 OE R/W t9 t11 ACK Figure 19. Timing Diagram – MUXed Synchronous Read Burst 3.3.7.2.3 MUXed Synchronous Write Burst Mode LPC_CLK t17 AD[31:0] (wr) t15 t15 t13 Address t18 ALE t5 TS t24 CSx R/W t14 t9 ACK Figure 20. Timing Diagram – MUXed Synchronous Write Burst MPC5121E/MPC5123 Data Sheet, Rev.
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Electrical and Thermal Characteristics 3.3.8 NFC The NAND flash controller (NFC) implements the interface to standard NAND Flash memory devices. This section describes the timing parameters of the NFC. NFC_CLE tCLH tCLS tCS tCH NFC_CE[1:0] tWP NFC_WE tALS tALH NFC_ALE tDS NFIO[7:0] tDH command Figure 21. Command Latch Cycle Timing NFC_CLE tCLS tCH tCS NFC_CE[1:0] tWC tWH tWP NFC_WE tALH tALS NFC_ALE tDS NFIO[7:0] tDH Address Figure 22.
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Electrical and Thermal Characteristics NFC_CLE tCLS tCS NFC_CE[1:0] tWC tWH tWP NFC_WE NFC_ALE tDS NFIO[15:0] tDH Data to NF Figure 23. Write Data Latch Timing NFC_CLE NFC_CE[1:0] tRC tREH tRP NFC_RE tAR tREA tRHZ NFC_ALE NFIO[15:0] Data from NF tRR R/B Figure 24. Read Data Latch Timing MPC5121E/MPC5123 Data Sheet, Rev.
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Electrical and Thermal Characteristics NFC_RE tss NFIO[15:0] NFC SYMMETRIC MODE(SYM=1) Figure 25. Read Data Latch Timing in Symmetric Mode Table 24. NFC Timing Characteristics in asymmetric mode(SYM=0)1 Timing parameter 1 Description Min. value Max. value Unit SpecID tCLS NFC_CLE setup Time T+1 — ns A8.1 tCLH NFC_CLE Hold Time T–1 — ns A8.2 tCS NFC_CE[1:0] Setup Time 2T – 1 — ns A8.3 tCH NFC_CE[1:0] Hold Time 3T — ns A8.4 tWP NFC_WP Pulse Width T–1 — ns A8.
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Electrical and Thermal Characteristics Table 25. NFC Timing Characteristics in Symmetric mode(SYM=1)1 Timing Parameter 3.3.9 Min. value Max. value Unit SpecID tCLS NFC_CLE Setup time T — ns A8.21 tCLH NFC_CLE Hold time T — ns A8.22 tCS NFC_CE[1:0] Setup time T-2 — ns A8.23 tCH NFC_CE[1:0] Hold time 1.5T-1 — ns A8.24 tWP NFC_WE Pulse width 0.5T+1 — ns A8.25 tALS NFC_ALE Setup time T — ns A8.26 tALH NFC_ALE Hold time T — ns A8.27 tDS Data Setup time 0.
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Electrical and Thermal Characteristics All ATA transfers are programmed in terms of system clock cycles ( IP bus clocks ) in the ATA Host Controller timing registers. This puts constraints on the ATA protocols and their respective timing modes in which the ATA Controller can communicate with the drive. Faster ATA modes ( i.e., UDMA 0, 1, 2 ) are supported when the system is running at a sufficient frequency to provide adequate data transfer rates.
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Electrical and Thermal Characteristics Table 3-26. PATA Timing Parameters (continued) Name Meaning Controlled by Value SpecID tskew4 Max difference in cable propagation delay between: ATA_IORDY and ATA_DATA (read) Cable A9.14 tskew5 Max difference in cable propagation delay between: ATA_DIOR, ATA_DIOW, ATA_DMACK and ATA_CS0, ATA_CS1, ATA_DA2, ATA_DA1, ATA_DA0, ATA_DATA (write) Cable A9.15 tskew6 Max difference in cable propagation delay without accounting for ground bounce Cable A9.16 3.3.
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Electrical and Thermal Characteristics Table 3-27. Timing Parameters PIO Read (continued) 1 ATA Parameter PIO Read Mode Timing Parameter t5 t5 t5(min) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 t6 t6 0 tA tA tA(min) = (1.5 + time_ax) × T –  (tco + tsui + tcable2 + tcable2 + 2 × tbuf) calculate and programming time_ax. 1 A9.25 trd trd1 trd1(max) = (–trd) + (tskew3 + tskew4) trd1(min) = (time_pio_rdx – 0.5 ) × T – (tsu + thi) (time_pio_rdx – 0.
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Electrical and Thermal Characteristics Table 3-28. Timing Parameters PIO Write PIO Write ATA Mode Timing Parameter Parameter 1 Value How to meet SpecID t1 t1 t1(min) = time_1 × T – (tskew1 + tskew2 + tskew5) time_1. 1 A9.30 t2 t2r t2(min) = time_2w × T – (tskew1 + tskew2 + tskew5) calculate and programming time_2w. 1 A9.31 t9 t9 t9(min) = time_9 × T – (tskew1 + tskew2 + tskew6) time_9. 1 A9.
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Electrical and Thermal Characteristics 3.3.9.3 Timing in Multiword DMA Mode Timing in multiword DMA mode is given in Figure 28 and Figure 29. tk1 DMARQ ADDR DMACK DIOR tm td tk tkjn Read Data (15:0) tgr tfr Figure 28. MDMA Read Timing tk1 DMARQ ADDR DMACK buffer_en DIOW tm ton td1 tk td tkjn toff Write Data (15:0) Figure 29. MDMA Write Timing To meet this timing, a number of timing parameters must be controlled as shown in Table 3-29. MPC5121E/MPC5123 Data Sheet, Rev.
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Electrical and Thermal Characteristics Table 3-29. Timing Parameters MDMA Read and Write 1 ATA Parameter MDMA Read/Write Timing Parameter tm, ti tm tm(min) = ti(min) = (time_m × T) – (tskew1 + tskew2 + tskew5) calculate and programming time_m. 1 A9.40 td td, td1 td1(min) = td(min) = (time_d × T) – (tskew1 + tskew2 + tskew6) calculate and programming time_d. 1 A9.41 tk tk tk(min) = (time_k × T) – (tskew1 + tskew2 + tskew6) calculate and programming time_k. 1 A9.
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Electrical and Thermal Characteristics tack ADDR DMARQ DMACK tenv DIOR DIOW tc1 tc1 IORDY Data Read tds tdh Figure 30. UDMA In Transfer Start Timing Diagram MPC5121E/MPC5123 Data Sheet, Rev.
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Electrical and Thermal Characteristics ADDR tack DMARQ DMACK DIOR trp DIOW tc1 tc1 tmli tx1 IORDY tmli tzah Data Read tds tzah tdh ton tdzfs tcvh toff Data Write buffer_en Figure 31. UDMA In Host Terminates Transfer ADDR tack DMARQ DMACK DIOR DIOW tmli tc1 tc1 tss1 tli5 IORDY tmli Data Read tds tdh tzah tzah ton tdzfs tcvh toff Data Write buffer_en Figure 32. UDMA In Device Terminates Transfer Timing parameters are explained in Table 30. MPC5121E/MPC5123 Data Sheet, Rev.
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Electrical and Thermal Characteristics Table 30. Timing Parameters UDMA in Burst ATA Parameter UDMA In Timing Parameter tack tack tenv Value How to Meet SpecID tack(min) = (time_ack × T) – (tskew1 + tskew2) calculate and programming time_ack. 1 A9.51 tenv tenv(min) = (time_env × T) – (tskew1 + tskew2) tenv(max) = (time_env × T) + (tskew1 + tskew2) calculate and programming time_env. 1 A9.52 tds tds1 tds – (tskew3) – ti_ds > 0 A9.
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Electrical and Thermal Characteristics tack ADDR DMARQ DMACK tenv DIOW DIOR tcyc tcyc buffer_en ton tdzfs tdvs tdvh tdvs Data Write tli1 IORDY trfs1 Figure 33. UDMA Out Transfer Start Timing Diagram ADDR tack DMARQ DMACK tss DIOW DIOR tcyc tli2 tcyc1 tdzfs_mli tcvh toff Data Write IORDY tli3 buffer_en Figure 34. UDMA Out Host Terminates Transfer MPC5121E/MPC5123 Data Sheet, Rev.
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Electrical and Thermal Characteristics r ADDR tack DMARQ tli2 DMACK DIOW DIOR trfs1 tcyc tdzfs_mli tcvh toff Data Write IORDY buffer_en Figure 35. UDMA Out Device Terminates Transfer Timing parameters are explained in Table 31. Table 31. Timing Parameters UDMA Out Burst ATA Parameter UDMA Out Timing Parameter tack tack tenv Value How to meet SpecID tack(min) = (time_ack × T) – (tskew1 + tskew2) calculate and program time_ack. 1 A9.
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Electrical and Thermal Characteristics Table 31. Timing Parameters UDMA Out Burst (continued) 1 ATA Parameter UDMA Out Timing Parameter tli tli2 tli2 > 0 — A9.74 tli tli3 tli3 > 0 — A9.75 tcvh tcvh tcvh = (time_cvh × T) – (tskew1 + tskew2) calculate and program time_cvh. 1 A9.76 — ton toff ton = time_on × T – tskew1 toff = time_off × T – tskew1 — A9.77 Value How to meet SpecID See the MPC5121e Microcontroller Reference Manual. 3.3.10 SATA PHY 1.
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Electrical and Thermal Characteristics Table 33. MII Tx Signal Timing Symbol Min Max Unit SpecID 5 TX_CLK rising edge to TXD [ 3 : 0 ], TX_EN, TX_ER invalid 3 — ns A11.5 6 TX_CLK rising edge to TXD [ 3 : 0 ], TX_EN, TX_ER valid — 25 ns A11.6 7 TX_CLK pulse width high 35% 65% TX_CLK Period1 A11.7 65% 1 A11.8 8 1 Description TX_CLK pulse width low 35% TX_CLK Period The TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g.
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Electrical and Thermal Characteristics 2 The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII characteristic) by programming the FEC MII_SPEED control register. See the MPC5121e/MPC5123 Reference Manual. 13 14 MDC (Output) 15 10 MDIO (Output) MDIO (Input) 11 12 Figure 39. Ethernet Timing Diagram – MII Serial Management MPC5121E/MPC5123 Data Sheet, Rev.
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Electrical and Thermal Characteristics 3.3.12 USB ULPI This section specifies the USB ULPI timing. For more information refer to UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1, October 20, 2004. Clock TSC THC TSD THD Control In (dir, nxt) Data In (8-bit) TDC TDC Control Out (stp) TDD Data Out (8-bit) Figure 40. ULPI Timing Diagram Table 36. Timing Specifications – ULPI Symbol Min Max Units SpecID 15 — ns A12.1 TSC, TSD Setup time (control in, 8-bit data in) — 6.0 ns A12.
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Electrical and Thermal Characteristics SD4 SD2 SD1 SD5 MMCx_CLK SD3 MMCx_CMD MMCx_DAT_0 Output from SDHC to card MMCx_DAT_1 MMCx_DAT_2 MMCx_DAT_3 SD6 MMCx_CMD MMCx_DAT_0 Input from card to SDHC MMCx_DAT_1 MMCx_DAT_2 MMCx_DAT_3 SD7 SD8 Figure 41. SDHC Timing Diagram Table 37 lists the timing parameters. . Table 37. MMC/SD Interface Timing Parameters ID Parameter Symbols Min Max Unit SpecID Card Input Clock Clock Frequency (Low Speed) fPP1 0 400 kHz A14.
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Electrical and Thermal Characteristics 3.3.15 DIU The DIU is a display controller designed to manage the TFT LCD display. 3.3.15.1 Interface to TFT LCD Panels, Functional Description Figure 42 shows the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with positive polarity. The sequence of events for active matrix interface timing is: • • • • DIU_CLK latches data into the panel on its positive edge (when positive polarity is selected).
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Electrical and Thermal Characteristics tHSP Start of line tPWH tFPH tSW tBPH tPCP DIU_CLK 11 Invalid Data DIU_LD[23:0] 2 3 DELTA_X Invalid Data DIU_HSYNC DIU_DE Figure 43. TFT LCD Interface Timing Diagram – Horizontal Sync Pulse Figure 44 shows the vertical timing (timing of one frame), including the vertical sync pulse and the data. All parameters shown in the diagram are programmable.
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Electrical and Thermal Characteristics Table 38. LCD Interface Timing Parameters – Pixel Level (continued) Name 1 Description Value Unit SpecID tFPH HSYNC Front Porch Width FP_H × tPCP ns A15.4 tSW Screen Width DELTA_X × tPCP ns A15.5 tHSP HSYNC (Line) Period (PW_H + BP_H + DELTA_X + FP_H) × tPCP ns A15.6 tPWV VSYNC Pulse Width PW_V × tHSP ns A15.7 tBPV VSYNC Back Porch Width BP_V × tHSP ns A15.8 tFPV VSYNC Front Porch Width FP_V × tHSP ns A15.
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Electrical and Thermal Characteristics 3.3.16 SPDIF The Sony/Philips Digital Interface (SPDIF) timing is totally asynchronous, therefore there is no need for relationship with the clock. 3.3.17 CAN The CAN functions are available as TX and CAN3/4_RX pins at normal IO pads and as CAN1/2 RX pins at the VBAT_RTC domain. There is no filter for the WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured. 3.3.
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Electrical and Thermal Characteristics NOTE Output timing is specified at a nominal 50 pF load. 6 2 5 SCL 3 1 4 7 9 8 SDA Figure 46. Timing Diagram – I2C Input / Output 3.3.19 J1850 See the MPC5121e/MPC5123 Reference Manual. 3.3.20 PSC The Programmable Serial Controllers (PSC) support different modes of operation (UART, Codec, AC97, SPI). UART is an asynchronous interface, there is no AC characteristic. 3.3.20.1 Codec Mode (8,16,24 and 32-bit)/I2S Mode Table 42.
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Electrical and Thermal Characteristics 1 BitClk Output (CLKPOL=0) 3 2 2 4 BitClk Output (CLKPOL=1) 4 5 3 FrameSync Output (SyncPol = 1) 6 FrameSync Output (SyncPol = 0) 7 TxD Output 8 RxD Input Figure 47. Timing Diagram – 8, 16, 24, and 32-bit CODEC/I2S Master Mode Table 43. Timing Specifications – 8, 16, 24, and 32-bit CODEC/I2S Slave Mode Symbol 1 1 Description Bit Clock cycle time Min Typ Max Units SpecID 40.0 — — ns A20.9 A20.
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Electrical and Thermal Characteristics 1 BitClk Input (CLKPOL=0) 2 2 BitClk Input (CLKPOL=1) FrameSync Input (SyncPol = 1) 3 FrameSync Input (SyncPol = 0) 4 TxD Output 5 RxD Input 6 Figure 48. Timing Diagram – 8,16, 24, and 32-bit CODEC/I2S Slave Mode 3.3.20.2 AC97 Mode Table 44. Timing Specifications – AC97 Mode Symbol Description Min Typ Max Units SpecID 1 Bit Clock cycle time — 81.4 — ns A20.15 2 Clock pulse high time — 40.7 — ns A20.16 3 Clock pulse low time — 40.
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Electrical and Thermal Characteristics 1 BitClk (CLKPOL=0) Input 4 FrameSync (SyncPol = 1) Output 5 3 2 Sdata_out Output 6 7 Sdata_in Input Figure 49. Timing Diagram – AC97 Mode 3.3.20.3 SPI Mode Table 45. Timing Specifications – SPI Master Mode, Format 0 (CPHA = 0) Symbol Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A20.26 2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A20.
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Electrical and Thermal Characteristics 1 SCK (CLKPOL=0) Output 2 10 2 11 SCK (CLKPOL=1) Output 11 10 9 8 3 SS Output 5 4 MOSI Output 6 6 MISO Input 7 7 Figure 50. Timing Diagram – SPI Master Mode, Format 0 (CPHA = 0) Table 46. Timing Specifications – SPI Slave Mode, Format 0 (CPHA = 0) Symbol Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A20.37 2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A20.
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Electrical and Thermal Characteristics 1 SCK (CLKPOL=0) Input 2 2 SCK (CLKPOL=1) Input 9 8 3 SS Input 5 4 MOSI Input 7 6 MISO Output Figure 51. Timing Diagram – SPI Slave Mode, Format 0 (CPHA = 0) Table 47. Timing Specifications – SPI Master Mode, Format 1 (CPHA = 1) Symbol Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A20.46 2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A20.
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Electrical and Thermal Characteristics 1 9 SCK (CLKPOL=0) Output 2 2 10 10 9 SCK (CLKPOL=1) Output 8 7 3 SS Output 4 MOSI Output 5 MISO Input 6 Figure 52. Timing Diagram – SPI Master Mode, Format 1 (CPHA = 1) Table 48. Timing Specifications – SPI Slave Mode, Format 1 (CPHA = 1) Symbol Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A20.56 2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A20.57 3 Slave select clock delay 0.
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Electrical and Thermal Characteristics 1 SCK (CLKPOL=0) Input 2 2 SCK (CLKPOL=1) Input 8 7 3 SS Input 5 6 MOSI Input 4 MISO Output Figure 53. Timing Diagram – SPI Slave Mode, Format 1 (CPHA = 1) 3.3.21 GPIOs and Timers The MPC5121e/MPC5123 contains several sets of I/Os that do not require special setup, hold, or valid requirements. The external events (GPIO or timer inputs) are asynchronous to the system clock.
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Electrical and Thermal Characteristics 3.3.23 IEEE 1149.1 (JTAG) Table 51. JTAG Timing Specification Symbol Characteristic Min Max Unit SpecID — TCK frequency of operation 0 25 MHz A23.1 1 TCK cycle time 40 — ns A23.2 2 TCK clock pulse width measured at 1.5 V 1.08 — ns A23.3 3 TCK rise and fall times 0 3 ns A23.4 1 4 TRST setup time to tck falling edge 10 — ns A23.5 5 TRST assert time 5 — ns A23.6 2 6 Input data setup time 5 — ns A23.
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Electrical and Thermal Characteristics TCK 4 TRST 5 Figure 55. Timing Diagram – JTAG TRST TCK 6 7 Input Data Valid Data Inputs 8 Output Data Valid Data Outputs 9 Data Outputs Figure 56. Timing Diagram – JTAG Boundary Scan TCK 10 11 Input Data Valid TDI, TMS 12 Output Data Valid TDO 13 TDO Figure 57. Timing Diagram – Test Access Port MPC5121E/MPC5123 Data Sheet, Rev.
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Electrical and Thermal Characteristics 3.3.24 VIU The Video Input Unit (VIU) is an interface which accepts the ITU656 format compatible video stream. Figure 58 shows the VIU interface timing and Table 52 lists the timing parameters. VIU_PIX_CLK fPIX_CLK tDHD tDSU VIU_DATA[9:0] Figure 58. VIU Interface Timing Diagram Table 52. VIU Interface Timing Parameters Parameter Min Typ Max Unit SpecID VIU Pixel Clock Frequency — — 83 MHz A24.1 tDSU VIU Data Setup Time 2.5 — — ns A24.
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System Design Information 4 System Design Information 4.1 Power Up/Down Sequencing Power sequencing between the 1.4 V power supply VDD_CORE and the remaining supplies is required to prevent excessive current during power up phase. The required power sequence is as follows: • • • • • 4.2 Use 12 V/millisecond or slower time for all supplies. Power up VDD_IO, PLL_AVDD, VBAT_RTC (if not applied permanently), VDD_MEM_IO, USB PHY, and SATA PHY supplies first in any order and then power up VDD_CORE.
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System Design Information The SATA PHY needs to be powered even if it is not used in an application. In this case, you should not enable the SATA oscillator and the SATA PHY by software. SATA_XTALI SATA_XTALO VSS NC NC NC SATA_ANAVIZ SATA_RESREF NC NC SATA_TXP SATA_TXN NC NC SATA_RXP SATA_RXN MPC5121e/ MPC5123 SATA_VDDA_3P3 SATA_VDDA_1P2 SATA_VDDA_VREG SATA_PLL_VDDA1P2 VDD_IO VDD_CORE 1.7–2.6 V VDD_CORE SATA_PLL_VSSA SATA_RX_VSSA SATA_TX_VSSA VSS VSS VSS Figure 60.
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System Design Information 4.4.2 Pull-Up Requirements for the PCI Control Lines PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to ensure that they contain stable values when no agent is actively driving the bus. This includes PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL, PCI_STOP, PCI_SERR, PCI_PERR, and PCI_REQ. Refer to the PCI Local Bus specification. 4.5 JTAG The MPC5121e/MPC5123 provides you with an IEEE 1149.
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System Design Information Table 53.
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System Design Information PORESET PORESET COP Header 13 11 HRESET 1 2 3 4 5 6 7 8 11 13 10 12 K VDD_IO 10 k 10 k SRESET VDD_IO 4 TRST TRST 14 9 10 k TMS VDD_IO TMS 12 7 9 HRESET VDD_IO SRESET 16 COP Connector Physical Pinout 10 k 3 VDD_IO VDD_IO 62 1 10 k TCK TCK TDO TDO 10 k TDI VDD_IO TDI 15 16 15 CKSTP_OUT 10 k VDD_IO CKSTP_OUT 8 CKSTP_IN 5 (3) halted 2 (4) qack 10 10 k VDD_IO CKSTP_IN (LPC_CLK) NC NC NC Figure 63. COP Connector Diagram 4.5.2.
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System Design Information PORESET HRESET SRESET PORESET 10 k HRESET VDD_IO 10 k VDD_IO SRESET TRST 10 k VDD_IO TMS 10 k VDD_IO TCK 10 k VDD_IO TDI CKSTP_OUT TDO Figure 64. TRST Wiring for Boards without COP Connector MPC5121E/MPC5123 Data Sheet, Rev.
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Package Information 5 Package Information This section details package parameters and dimensions. The MPC5121e/MPC5123 is available in a Thermally Enhanced Plastic Ball Grid Array (TEPBGA), see Section 5.1, “Package Parameters,” and Section 5.2, “Mechanical Dimensions,” for information on the TEPBGA. 5.1 Package Parameters Table 54. TEPBGA Parameters 5.2 Package outline 27 mm  27 mm Interconnects 516 Pitch 1.00 mm Module height (typical) 2.25 mm Solder Balls 96.5 Sn/3.
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Package Information Figure 65. Mechanical Dimension and Bottom Surface Nomenclature of the MPC5121e/MPC5123 TEPBGA 1 All dimensions are in millimeters. Dimensions and tolerances per ASME Y14.5M-1994. 3 Maximum solder ball diameter measured parallel to datum A. 4 Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 2 MPC5121E/MPC5123 Data Sheet, Rev.
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Product Documentation 6 Product Documentation This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com. Table 55 provides a revision history for this document. Table 55. Document Revision History Revision Substantive Change(s) Rev. 0, DraftA First Draft (5/2008) Rev. 0, DraftB Second Draft (5/2008) Rev. 0, DraftC Third Draft (7/2008) Rev. 1 Advance Information (10/2008) Rev.
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How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.