Datasheet

Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 23
3.1.4 Electrostatic Discharge
CAUTION
This device contains circuitry that protects against damage due to high-static voltage or
electrical fields. However, it is advised that normal precautions be taken to avoid
application of any voltages higher than maximum-rated voltages. Operational
reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (GND
or VDD
). Table 10 gives package thermal characteristics for this device.
3.1.5 Power Dissipation
Power dissipation of the MPC5121e/MPC5123 is caused by 4 different components: the dissipation of the internal or core
digital logic (supplied by V
DD_CORE)
, the dissipation of the analog circuitry (supplied by SYS_PLL_AVDD and
CORE_PLL_AVDD), the dissipation of the IO logic (supplied by V
DD_MEM_IO
and V
DD_IO
) and the dissipation of the PHYs
(supplied by own supplies).
Table 9 details typical measured core and analog power dissipation figures for a range of operating
modes. However, the dissipation due to the switching of the IO pins can not be given in general, but must be calculated for each
application case using the following formula:
Eqn. 1
where N is the number of output pins switching in a group M, C is the capacitance per pin, V
DD_IO
is the IO voltage swing, f
is the switching frequency and P
IOint
is the power consumed by the unloaded IO stage. The total power consumption of the
device must not exceed the value that would cause the maximum junction temperature to be exceeded.
Eqn. 2
Table 8. ESD and Latch-Up Protection Characteristics
Symbol Rating Min Max Unit SpecID
V
HBM
Human Body Model (HBM) – JEDEC JESD22-A114-B 2000 — V D4.1
V
MM
Machine Model (MM) – JEDEC JESD22-A115 200 — V D4.2
V
CDM
Charge Device Model (CDM) – JEDEC JESD22-C101 500 — V D4.3
Table 9. Power Dissipation
Core Power Supply (V
DD_CORE
)
SpecID
Mode
High-Performance
Unit
e300 = 300 MHz, CSB = 200 MHz
Operational
1
800 mW D5.1
Deep-Sleep
1
1 mW D5.2
Hibernation 20 uW D5.3
PLL/OSC Power Supplies (SYS_PLL_AVDD, CORE_PLL_AVDD)
Typical 25 mW D5.4
Unloaded I/O Power Supplies (V
DD_IO
, V
DD_MEM_IO
)
P
IO
P
IOint
N
M

+ CVDD_IO
2
f=
P
total
P
core
P
analog
P
IO
PPHYs+++=