Datasheet

MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor26
from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling
effects of the thermocouple wire.
3.2 Oscillator and PLL Electrical Characteristics
The MPC5121e/MPC5123 System requires a system-level clock input SYS_XTALI. This clock input may be driven directly
from an external oscillator or with a crystal using the internal oscillator.
There is a separate oscillator for the independent Real Time Clock (RTC) system.
The MPC5121e/MPC5123 clock generation uses two phase locked loop (PLL) blocks.
• The system PLL (SYS_PLL) takes an external reference frequency and generates the internal system clock. The
system clock frequency is determined by the external reference frequency and the settings of the SYS_PLL
configuration.
• The e300 core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The e300 core clock frequency
is determined by the system clock frequency and the settings of the CORE_PLL configuration.
The USB PHY contains its own oscillator with the input USB_XTALI and an embedded PLL.
The SATA PHY contains its own oscillator with the input SATA_XTALI and an embedded PLL.
3.2.1 System Oscillator Electrical Characteristics
The system oscillator can work in oscillator mode or in bypass mode to support an external input clock as clock reference.
Figure 3. Timing Diagram—SYS_XTALI
Table 11. System Oscillator Electrical Characteristics
Characteristic Symbol Min Typical Max Unit SpecID
SYS_XTALI frequency f
sys_xtal
15.6 33.3 35.0 MHz O1.1
Table 12. SYS_XTALI Timing
Sym Description Min Max Units SpecID
t
CYCLE
SYS_XTALI cycle time
1, 2
1
The SYS_XTALI frequency and system PLL settings must be chosen such that the resulting system frequencies do not exceed
their respective maximum or minimum operating frequencies. See the MPC5121e Microcontroller Reference Manual.
2
The MIN/Max cycle times are calculated using 1/f
sys_xtal (MIN/MAX)
where the f
sys_xtal (MIN/MAX)
(15.6/35 MHz) are taken from
Table 11.
64.1 28.57 ns O.1.2
t
RISE
SYS_XTALI rise time
3
3
Rise time is measured from 20% of vdd to 80% of V
DD
.
1 4 ns O.1.3
t
FALL
SYS_XTALI fall time
4
1 4 ns O.1.4
t
DUTY
SYS_XTALI duty cycle
5
40 60 % O.1.5
t
FALL
t
RISE
t
CYCLE
SYS_XTALI CLK
t
DUTY
t
DUTY
CV
IH
CV
IL
V
M
V
M
V
M