Datasheet

Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 27
3.2.2 RTC Oscillator Electrical Characteristics
3.2.3 System PLL Electrical Characteristics
3.2.4 e300 Core PLL Electrical Characteristics
The internal clocking of the e300 core is generated from and synchronized to the system clock by means of a voltage-controlled
core PLL.
4
Fall time is measured from 20% of vdd to 80% of V
DD
.
5
SYS_XTALI duty cycle is measured at V
M
.
Table 13. RTC Oscillator Electrical Characteristics
Characteristic Symbol Min Typical Max Unit SpecID
RTC_XTALI frequency f
rtc_xtal
— 32.768 — kHz O2.1
Table 14. System PLL Specifications
Characteristic Symbol Min Typical Max Unit SpecID
Sys PLL input clock frequency
1
1
The SYS_XTALI frequency and PLL Configuration bits must be chosen such that the resulting system frequency, CPU (core)
frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies.
f
sys_xtal
16 33.3 67 MHz O3.1
Sys PLL input clock jitter
2
2
This represents total input jitter—short term and long term combined. Two different types of jitter can exist on the input to
CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected. Systemic jitter is passed into and through the
PLL to the internal clock circuitry.
t
jitter
— — 10 ps O3.2
Sys PLL VCO frequency

f
VCOsys
400 — 800 MHz O3.3
Sys PLL VCO output jitter (Dj), peak to peak / cycle f
VCOjitterDj
— — 40 ps O3.4
Sys PLL VCO output jitter (Rj), RMS 1 sigma f
VCOjitterRj
— — 12 ps O3.5
Sys PLL relock time—after power up
3
3
PLL relock time is the maximum amount of time required for the PLL lock after a stable VDD and CORE_SYSCLK are reached
during the power-on reset sequence.
t
lock1
— — 200 s O3.6
Sys PLL relock time—when power was on
4
4
PLL relock time is the maximum amount of time required for the PLL lock after the PLL has been disabled and subsequently
re-enabled during sleep modes.
t
lock2
— — 170 s O3.7
Table 15. e300 PLL Specifications
Characteristic Symbol Min Typical Max Unit SpecID
e300 frequency
1
f
core
200 — 400 MHz O4.1
e300 PLL VCO frequency
1
f
VCOcore
400 — 800 MHz O4.3
e300 PLL input clock frequency f
CSB_CLK
50 — 200 MHz O4.4
e300 PLL input clock cycle time t
CSB_CLK
5 — 20 ns O4.5
e300 PLL relock time
2
t
lock
— — 200 s O4.6