Datasheet

MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor30
NOTES:
1. The SYS_XTALI frequency, Sys PLL, and CORE PLL settings must be chosen so that the resulting e300 clk, csb_clk, MCK,
frequencies do not exceed their respective maximum or minimum operating frequencies.
2. The values are valid for the user operation mode. There can be deviations for test modes.
3. The selection of the peripheral clock frequencies needs to take care about requirements for baud rates and minimum frequency
limitation.
4.The DDR data rate is 2× the DDR memory bus frequency.
See the MPC5121e Microcontroller Reference Manual for more information on the clock subsystem.
3.3.3 Resets
The MPC5121e/MPC5123 has three reset pins:
• PORESET—Power on Reset
• HRESET—Hard Reset
• SRESET—Software Reset
These signals are asynchronous I / O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires
the same input characteristics as other MPC5121e/MPC5123 inputs, as specified in
Section 3.1, “DC Electrical
Characteristics.”
As long as V
DD
is not stable the HRESET output is not stable.
The timing relationship is shown in Figure 4.
NFC Clock 2.08 83 MHz A1.7
DIU Clock 0.78 100 MHz A1.8
SDHC Clock 0.78 66.6 MHz A1.9
MBX Clock 6.25 100 MHz A1.10
Table 17. Reset Rise / Fall Timing
Description Min Max Unit SpecID
PORESET
1
fall time
1
Make sure that the PORESET does not carry any glitches. The
MPC5121e/MPC5123 has no filter to prevent them from getting into the chip.
— 1 ms A3.4
PORESET rise time — 1 ms A3.5
HRESET
2,3
fall time
2
HRESET and SRESET must have a monotonous rise time.
3
The assertion of HRESET becomes active at Power on Reset without any
SYS_XTALI clock.
— 1 ms A3.6
HRESET rise time — 1 ms A3.7
SRESET fall time — 1 ms A3.8
SRESET rise time — 1 ms A3.9
Table 16. Clock Frequencies (continued)
Min Max Units SpecID