Datasheet

MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor32
Figure 6. HRESET Behavior
Figure 7. SRESET Behavior
Table 18. Reset Timing
Symbol Description
Value
SYS_XTALI
SpecID
t
PORHOLD
Time PORESET must be held low before a qualified reset occurs 4 cycles A3.10
t
HRVAL
Time HRESET is asserted after a qualified reset occurs 26810 cycles A3.11
t
SRVAL
Time SRESET is asserted after assertion of HRESET 32 cycles A3.12
t
EXEC
Time between SRESET assertion and first core instruction fetch 4 cycles A3.13
SYS_XTALI
PORESET
SRESET
HRESET
RST_CONF[31:0]
ADDR[31:0]
t
SRVAL
t
EXEC
t
HRVAL
t
HRHOLD
t
HR_SR_Delay
no new fetch of the RST_CONF
SYS_XTALI
PORESET
SRESET
HRESET
RST_CONF[31:0]
ADDR[31:0]
t
EXEC
t
SRMIN
t
SRHOLD
no new fetch of the RST_CONF