Datasheet

MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor34
3.3.5.1 DDR and DDR2 SDRAM AC Timing Specifications
Figure 8 shows the DDR SDRAM write timing.
Figure 8. DDR Write Timing
Figure 9 and Figure 10 shows the DDR SDRAM read timing.
Table 20. DDR and DDR2 (DDR2-400) SDRAM Timing Specifications
At recommended operating conditions with V
DD_MEM_IO
of 5%
Parameter Symbol Min Max Unit Notes SpecID
Clock cycle time, CL=x t
CK
5000 — ps A5.1
CK HIGH pulse width t
CH
0.47 0.53 t
CK
1
,
2
1
Measured with clock pin loaded with differential 100 termination resistor.
2
All transitions measured at mid-supply (VDD_MEM_IO/2).
A5.3
CK LOW pulse width t
CL
0.47 0.53 t
CK
1
,
2
A5.4
Skew between MCK and DQS
transitions
t
DQSS
0.25 0.25 t
CK
2
,
3
3
Measured with all outputs except the clock loaded with 50 termination resistor to V
DD_MEM_IO
/2.
A5.5
Address and control output setup
time relative to MCK rising edge
t
OS(base)
(t
CK
/2 – 750) — ps
2
,
3
A5.6
Address and control output hold
time relative to MCK rising edge
t
OH(base)
(t
CK
/2 – 750) — ps
2
,
3
A5.7
DQ and DM output setup time
relative to DQS
t
DS1(base)
(t
CK
/4 – 500) — ps
2
,
3
A5.8
DQ and DM output hold time relative
to DQS
t
DH1(base)
(t
CK
/4 – 500) — ps
2
,
3
A5.9
DQS-DQ skew for DQS and
associated DQ inputs
t
DQSQ
–(t
CK
/4 – 600) (t
CK
/4 – 600) ps
2
A5.10
DQS window start position related to
CAS read command
t
DQSEN
TBD TBD ps
1
,
2
,
3
,
4
,
5
4
In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low.
5
Window position is given for t
DQSEN
= 2.0 t
CK.
For other values of t
DQSEN,
window position is shifted accordingly.
A5.11

MCK
t
CH
t
CL
DQS
t
DQSS
DQ, DM(out)
t
DS
t
DH
t
CK