Datasheet

MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor36
Figure 12. PCI CLK Waveform
2
Table 21. PCI CLK Specifications
Sym Description
66 MHz
1
1
In general, all 66 MHz PCI components must work with any clock frequency up to 66 MHz. CLK
requirements vary depending upon whether the clock frequency is above 33 MHz.
33 MHz
Units SpecID
Min
2
2
Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met
across the minimum peak-to-peak portion of the clock waveform as shown in Figure 12.
Max Min Max
t
cyc
PCI CLK Cycle Time
1,3
3
The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system
jitter.
15 30 30 — ns A6.1
t
high
PCI CLK High Time 6 — 11 — ns A6.2
t
low
PCI CLK Low Time 6 — 11 — ns A6.3
— PCI CLK Slew Rate
2
1.5 4 1 4 V/ns A6.4
Table 22. PCI Timing Parameters
1
1
See the timing measurement conditions in the PCI Local Bus Specification. It is important that all driven
signal transitions drive to their Voh or Vol level within one Tcyc.
Sym Description
66 MHz 33 MHz
Units SpecID
Min
2
2
Minimum times are measured at the package pin with the load circuit, and maximum times are measured
with the load circuit as shown in the PCI Local Bus Specification.
Max Min Max
t
val
CLK to Signal Valid Delay –
bused signals
1,2,3
2 6 2 11 ns A6.5
t
val
(ptp) CLK to Signal Valid Delay – point
to point
1,2,3
2 6 2 12 ns A6.6
t
on
Float to Active Delay
1
2 — 2 — ns A6.7
t
off
Active to Float Delay
1
14 28 ns A6.8
t
su
Input Setup Time to CLK – bused
signals
3,4
3 — 7 — ns A6.9
t
su
(ptp) Input Setup Time to CLK – point
to point
3,4
3
REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT#
and REQ# have a setup of 5 ns at 66 MHz. All other signals are bused.
5 — 10,12 — ns A6.10
t
h
Input Hold Time from CLK
4
0 — 0 — ns A6.11
t
cyc
PCI CLK
t
low
t
high
0.4Vcc
0.4Vcc, p-to-p
0.3Vcc
0.5Vcc
0.6Vcc
0.2Vcc
(minimum)