Datasheet

Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 37
For Measurement and Test Conditions, see the PCI Local Bus Specification.
3.3.7 LPC
The Local Plus Bus is the external bus interface of the MPC5121e/MPC5123. A maximum of eight configurable chip selects
(CS) are provided. There are two main modes of operation: non-MUXed and MUXED. The reference clock is the LPC CLK.
The maximum bus frequency is 83
MHz.
Definition of Acronyms and Terms:
WS = Wait State
DC = Dead Cycle
HC = Hold Cycle
DS = Data Size in Bytes
BBT = Burst Bytes per Transfer
AL = Address latch enable Length
ALT = Chip select/Address Latch Timing
t
LPCck
= LPC clock period
4
See the timing measurement conditions in the PCI Local Bus Specification.
Table 23. LPC Timing
Sym Description Min Max Units SpecID
t
OD
CS[x], ADDR, R/W, TSIZ, DATA (wr),
TS, OE valid after LPC CLK
(Output Delay related to LPC CLK)
0 5 ns A7.1
t
1
Non-MUXed non-Burst CS[x] pulse
width
(2 + WS) × t
LPCck
(2 + WS) × t
LPCck
ns A7.2
t
2
ADDR, R/W, TSIZ, DATA (wr) valid
before CS[x] assertion
t
LPCck
– t
OD
t
LPCck
+ t
OD
ns A7.3
t
3
OE assertion after CS[x] assertion t
LPCck
– t
OD
t
LPCck
+ t
OD
ns A7.4
t
4
ADDR, R/W, TSIZ, Data (wr) hold after
CS[x] negation
t
LPCck
– t
OD
(HC + 1) × t
LPCck
+ t
OD
ns A7.5
t
5
TS pulse width t
LPCck
t
LPCck
ns A7.6
t
6
DATA (rd) setup before LPC CLK 4 — ns A7.7
t
7
DATA (rd) input hold 0 (DC + 1) × t
LPCck
ns A7.8
t
8
Non-MUXed read Burst CS[x] pulse
width
(2 + WS + BBT/DS) × t
LPCck
(2 + WS + BBT/DS) × t
LPCck
ns A7.9
t
9
Burst ACK pulse width (BBT/DS) × t
LPCck
(BBT/DS) × t
LPCck
ns A7.10
t
10
Burst DATA (rd) input hold 0 — ns A7.11
t
11
Read Burst ACK assertion after CS[x]
assertion
(2 + WS) × t
LPCck
(2 + WS) × t
LPCck
ns A7.12
t
12
Non-muxed write Burst CS[x] pulse
width
(2.5 + WS + BBT/DS) × t
LPCck
(2.5 + WS + BBT/DS) × t
LPCck
ns A7.13
t
13
Write Burst ADDR, R/W, TSIZ, DATA
(wr) hold after CS[x] negation
0.5 × t
LPCck
– t
OD
(HC + 0.5) × t
LPCck
+ t
OD
ns A7.14